Patents by Inventor Dilip Lalwani

Dilip Lalwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5619511
    Abstract: The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: April 8, 1997
    Assignee: Intel Corporation
    Inventors: Junji Sugisawa, Dilip Lalwani