Abstract: A semiconductor structure includes a gate electrode disposed above a semiconductor substrate of a first conductivity type. The semiconductor structure further includes a source region of the first conductivity type positioned, at least partially, below the gate electrode, and a doped region of a second conductivity type, opposite to the first conductivity type, located adjacent to the source region. The semiconductor structure further includes a first ohmic contact positioned above and in contact with the source region and the doped region. The first ohmic contact having a length and a contact area in electrical communication with the doped region. The semiconductor structure further includes a field oxide adjacent to the doped region, with the length of the first ohmic contact extending above the doped region until a distance between the first ohmic contact and the field oxide is equal to a threshold value.

Abstract: A method of forming a semiconductor device includes forming a first oxide layer having a first thickness to line a trench formed in a Silicon Carbide (SiC) substrate. The method further includes etching the first oxide layer to form a second oxide layer having the first thickness. A portion of the trench lined by the second oxide layer being less than a portion of the trench lined by the first oxide layer. The method further includes forming a third oxide layer having a second thickness on the trench and on a top surface of the second oxide layer. A combination of the second oxide layer and the third oxide layer forming an oxide region that lines different portions of the trench with different oxide thickness. The method further includes forming a gate electrode in the trench lined with the oxide region.

Abstract: A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper and bottom surface. A drift region of the first conductivity type is located on the upper surface. Above the drift region, a channel region of a second conductivity type, opposite to the first conductivity type, is located featuring a hybrid configuration. The hybrid configuration includes a first channel segment of a first channel geometry located between and directly connected to two second channel segments of a second channel geometry. A source region of the first conductivity type is located adjacent to the channel region. A first doped semiconductor region of the second conductivity type, featuring a third geometry, is placed above the drift region and adjacent to the first channel segment. Finally, a gate electrode is located above the drift region via a gate oxide.

Abstract: A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type, opposite to the first conductivity type, located above the drift layer, and a source region of the first conductivity type located above the channel layer. The semiconductor structure further includes a stepped shaped trench structure that extends through the source region and the channel layer until a top portion of the drift layer, a gate electrode located within the trench structure and surrounded by a gate insulating film, and a shield region of the second conductivity type covering a bottom of the trench structure such that the shield region extends laterally along the trench structure to a trench corner.

Abstract: A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper surface and a bottom surface. The semiconductor structure further includes a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The upper surface having a transistor region and peripheral regions located at each corner of the transistor region. The transistor region further includes a channel region of a second conductivity type, opposite to the first conductivity type, located above the drift region and positioned on a center portion of the transistor region, a source region of the first conductivity type adjacent to the channel region, and a gate electrode located above the drift region via a gate oxide, the gate electrode surrounds the source region. Each of the peripheral regions includes a first semiconductor region of the second conductivity type formed above the drift region.

Abstract: A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type, having an upper surface and a bottom surface. A drift layer of the first conductivity type is positioned on the upper surface of the semiconductor substrate. A pair of source regions of the first conductivity type is disposed on the drift layer. A first semiconductor region of the first conductivity type disposed on a center portion of the drift layer is sandwiched between the pair of source regions. Laterally abutting a bottom portion of the first semiconductor region is a pair of second semiconductor regions of a second conductivity type opposite to the first conductivity. Embedded within the first semiconductor region is a third semiconductor region of the second conductivity type. An oxide layer is located, at least partially, within the first semiconductor region, extending above an upper surface of the first semiconductor region.

Abstract: A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

Abstract: A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type located above the drift layer, and a source region of the first conductivity type located above the channel layer. The second conductivity type is opposite to the first conductivity type. A plurality of trenches penetrates through the source region, the channel layer and a portion of the drift region. A gate electrode is located within each of the plurality of trenches via a gate insulating film and a plurality of shielding structures of the second conductivity type is located around the gate electrode. The plurality of shielding structures covers sidewalls and a bottom of the plurality of trenches. The plurality of shielding structures is arranged in an island-like manner.

Abstract: Semiconductor devices and processes for manufacturing semiconductors are described. A semiconductor device can include a drift region formed on a Silicon Carbide substrate. The semiconductor device can include a trench that penetrates through a source region and a channel and reaches the drift region. The semiconductor device can include an oxide region lining the trench. The oxide region can include a bottom portion, a lower side portion and an upper side portion. A thickness of the bottom portion and a thickness of the lower side portion can be greater than a thickness of the upper side portion. The semiconductor device can include a gate electrode formed in the trench lined with the oxide region. The semiconductor device can include a shield region in contact with a bottom portion of the trench. A width of the semiconductor region can be less than or equal to a width of the trench.

Abstract: A vertical silicon carbide transistor is provided in which a body contact and a source contact are both formed at an upper surface of a silicon carbide layer. The source contact and the body contact are wet etched so that a sidewall of the etched source contact is spaced apart and above an upper surface of the etched body contact. A silicide layer forms a buried contact to the body contact and also couples to the sidewall of the source contact.

Abstract: An integrated structure (1) comprising a high-electron-mobility transistor (HEMT) (3) and a temperature sensing arrangement (8) integrated with the HEMT, the temperature sensing element (7) configured to provide a signal indicative of temperature for providing temperature protection for the HEMT.