Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Abstract: A charge storage device is resistant to degradation in reducing atmospheres for use in dynamic random access memories. The device consists of a dielectric layer that is sandwiched between two electrodes and grown on a suitable substrate such as silicon or silicon coated with silicon dioxide. The dielectric layer is either (a) a modified composition of Ba.sub.x Sr.sub.1-x TiO.sub.3, 0<x<1 (BST) doped with acceptor type dopants such as Mn, Co, Mg, Cr, Ga and Fe ions as the dielectric layer in the capacitor; the acceptor ions can occupy the titanium sites to prevent the formation of Ti.sup.3+ and inhibit the formation of conductive BST by compensating the charges of the oxygen vacancies, and by trapping the free electrons more freely than Ti.sup.4+, or (b) modified dielectric compositions with alkaline-earth ions with compositions [(Ba.sub.x M.sub.x)O].sub.y TiO.sub.2 (where M can be Ca, Sr or Mg) with the value of y slightly larger than unity.

Abstract: A ferroelectric capacitor device and method of manufacture. A substrate supports a bottom electrode structure, with an adhesion/diffusion barrier layer sandwiched therebetween. The electrode layer includes a metal or metal alloy and an oxide of the metal or alloy. The adhesion/diffusion barrier layer is a similar oxide. Ferroelectric material is sandwiched between a top electrode. The top layer includes a metal or metal alloy and an oxide of the same; the metal or metal alloy may be the same as the bottom electrode but need not be. The metal and metal oxide electrodes may be deposited by known deposition techniques, or the metal may be deposited and the oxide formed by annealing in oxygen ambient environment.

Abstract: A capacitor for use on silicon or other substrate has a multilayer electrode structure. In a preferred embodiment, a bottom electrode situated on the substrate has a bottom layer of Pt--Rh--O.sub.x, an intermediate layer of Pt--Rh, and a top layer of Pt--Rh--O.sub.x. A ferroelectric material such as PZT (or other material) is situated on the bottom electrode. A top electrode, preferably of identical composition as the bottom electrode, is situated on the opposite side of the ferroelectric from the bottom electrode.

Abstract: A method of reactive ion etching both a lead zirconate titanate ferroelectric dielectric and a RuO.sub.2 electrode, and a semiconductor device produced in accordance with such process. The dielectric and electrode are etched in an etching gas of O.sub.2 mixed with either CClF.sub.2 or CHClFCF.sub.3.

Abstract: A ferroelectric device is constructed using a bottom electrode composed of a conducting oxide such as RuO.sub.x, on a substrate such as silicon or silicon dioxide. A ferroelectric material such as lead zirconate titanate (PZT) is deposited on the bottom electrode, and a conducting interlayer is formed at the interface between the ferroelectric and the electrode. This interlayer is created by reaction between the materials of the ferroelectric and electrode, and in this case would be Pb.sub.2 Ru.sub.2 O.sub.7-x. A conductive top layer is deposited over the ferroelectric. This top layer may be a metal, or it may be the same type of materials as the bottom electrode, in which case another interlayer can be formed at the interface. A device constructed in this manner has the property of lower degradation due to fatigue, breakdown, and aging.