Abstract: A class AB buffer (or amplifier) is disclosed for driving a large capacitive load. The disclosed CMOS class AB buffer can drive capacitive loads, for example, in excess of 100 pF, while operating from a voltage supply as low as 1.5 volts. The disclosed class AB buffer includes a pair of driving transistors that are cross-coupled through an amplifier and level shifting circuitry, such as transistor circuitry, and a pair of current source transistors each having a gate terminal connected to an output of the corresponding amplifier and a gate terminal of an output transistor, and a drain terminal connected to a source terminal of the driving transistors. The driving transistors are prevented from entering a linear region by connecting a drain terminal of each of the driving transistors to a positive power supply voltage. The threshold voltage of only one transistor must be overcome before the transistors conduct current, since the gate-sources of the driving and current source transistors are not in series.

Abstract: The common-mode feedback circuit generates currents representing the output voltages of a fully differential amplifier, and sums these current to produce a summation current. Based on the comparison of the summation current to a reference current, the common-mode feedback circuit generates a feedback voltage for stabilizing the fully differential amplifier.

Abstract: A class AB buffer (or amplifier) is disclosed for driving a large capacitive load. The disclosed CMOS class AB buffer can drive capacitive loads, for example, in excess of 100 pF, while operating from a voltage supply as low as 1.5 volts. The disclosed class AB buffer includes a pair of driving transistors that are cross-coupled through an amplifier and level shifting circuitry, such as transistor circuitry, and a pair of current source transistors each having a gate terminal connected to an output of the corresponding amplifier and a gate terminal of an output transistor, and a drain terminal connected to a source terminal of the driving transistors. The driving transistors are prevented from entering a linear region by connecting a drain terminal of each of the driving transistors to a positive power supply voltage. The threshold voltage of only one transistor must be overcome before the transistors conduct current, since the gate-sources of the driving and current source transistors are not in series.

Abstract: The common-mode feedback circuit generates currents representing the output voltages of a fully differential amplifier, and sums these current to produce a summation current. Based on the comparison of the summation current to a reference current, the common-mode feedback circuit generates a feedback voltage for stabilizing the fully differential amplifier.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: Improved linearity in a line driver amplifier is realized by employing one or more amplifier sections each including an adaptive gain amplifier connected in parallel with a distributed gain amplifier. In an embodiment of the invention, first and second amplifier sections are connected in circuit relationship to an input and an output of the line driver amplifier to form a symmetrical amplifier configuration. In a specific embodiment of the invention, the adaptive gain amplifiers in each amplifier section are class AB type amplifiers and the distributed gain amplifiers in each amplifier section are class B amplifiers. Specifically, each of the distributed gain class B amplifiers each include a plurality of output transistors and a corresponding plurality of auxiliary amplifiers. The output transistor and auxiliary amplifier pairs are connected in parallel.

Abstract: In a class AB amplifier circuit for use in an integrated circuit (IC) device, a bias circuit is used to bias a first field effect transistor (FET) in an output stage. A second FET in the bias circuit is connected to the first FET. The drain current of the first FET contributes to the output of the amplifier circuit. In response to a difference in inputs to the amplifier circuit in a transient state, the second FET operates in a non-saturation mode especially when the voltage of the power supply to the amplifier circuit is required to be low, e.g., 2 volts. As a result, an input voltage to the first FET which operates in a saturation mode increases, thereby increasing its drain current contributing to the amplifier circuit output. This increased drain current advantageously prevents the otherwise significant distortion in the amplifier circuit output during the transient state.

Abstract: A line driver amplifier is implemented by employing amplifier stages including a plurality of output transistors and a corresponding plurality of auxiliary amplifiers. The output transistor and auxiliary amplifier pairs are connected in parallel. Each of the auxiliary amplifiers includes a built in voltage offset, beginning with an auxiliary amplifier having the smallest voltage offset to the auxiliary amplifier having the largest offset. The individual auxiliary amplifiers maintain their corresponding output transistors in an OFF state so long as the overall amplifier input signal has a magnitude less than the auxiliary amplifier offset voltage level. When the input signal magnitude level is equal to or greater than the offset voltage level of an auxiliary amplifier, that auxiliary amplifier turns its corresponding output transistor to an ON state.

Abstract: A tunable integrator circuit having a main amplifier with an input resistor R and a feedback capacitor C and a tuning amplifier having a variable gain k between the output of the main amplifier and the feedback capacitor. The circuit has an effective capacitance of kC. Thus the integrator can be tuned to compensate for temperature and processing variations of the RC product by adjusting the gain of the tuning amplifier. The tuning amplifier can also be used to multiply the effective capacitance of the filter, kC, by increasing the gain k of the tuning amplifier beyond that needed to compensate for RC variations, thus reducing the area required for on-chip capacitances while maintaining a constant resistance. The circuit can be used independently or in conjunction with a capacitor array.

Abstract: A tuning circuit for generating a digital code to be used to calibrate a capacitor array of the type used in active RC filters is comprised of a single-slope A/D converter with fixed reference voltages as inputs and an output value which is dependent on the RC product of a resistor and capacitor within the converter. A decoder converts the RC product as measured by the A/D converter into a digital code which, when applied to the appropriate capacitor array, sets the array capacitance to compensate for the difference between the measured RC product and the nominal design value.

Abstract: A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.