Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

Abstract: A method of memory deduplication includes identifying hash tables each corresponding to a hash function, and each including physical buckets, each physical bucket including ways and being configured to store data, identifying virtual buckets each including some physical buckets, and each sharing a physical bucket with another virtual bucket, identifying each of the physical buckets having data stored thereon as being assigned to a single virtual bucket, hashing a data line according to a hash function to produce a hash value, determining whether a corresponding virtual bucket has available space for a block of data according to the hash value, sequentially moving data from the corresponding virtual bucket to an adjacent virtual bucket when the corresponding virtual bucket does not have available space until the corresponding virtual bucket has space for the block of data, and storing the block of data in the corresponding virtual bucket.

Abstract: A memory system may comprise a plurality of data strobe transfer paths assigned to a plurality of data transfer paths such that each of the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths. At least one selected data strobe transfer path is selected and data signals transferred through the plurality of data transfer paths are sampled using at least one data strobe signal transferred through the selected data strobe transfer path. Reliability of data communication is enhanced through a redundant data strobe scheme by assigning a plurality of data strobe transfer paths to a plurality of data transfer paths such that the plurality of data strobe transfer paths may be shared by the plurality of data transfer paths.

Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.

Abstract: A data chip that may pollute data is disclosed. The data chip may include a data array, read circuitry to read raw data from the data array, and a buffer to store the raw data. Using a pollution pattern stored in a mask register, a data pollution engine may pollute the raw data. Transmission circuitry may then transmit the polluted data.

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array having a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows; and a controller that may be coupled to the at least one computing cell array to configure the at least one computing cell array to perform a DPU operation.

Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.

Abstract: A system includes a library, a compiler, a driver and at least one dynamic random access memory (DRAM) processing unit (DPU). The library may determine at least one DPU operation corresponding to a received command. The compiler may form at least one DPU instruction for the DPU operation. The driver may send the at least one DPU instruction to at least one DPU. The DPU may include at least one computing cell array that includes a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

Abstract: A method of storing data in a memory module including an in-module prefetcher, an in-module prefetch buffer, memory, and a memory controller, the method including sending address information from the in-module prefetcher to the memory controller and to the prefetch buffer, determining prefetch accuracy based on a comparison of the address information sent to the memory controller and the address information sent to the prefetch buffer, determining a prefetch mode based on the prefetch accuracy, and storing the data in the memory based on the prefetch mode.

Abstract: A dynamic random access memory (DRAM) processing unit (DPU) may include at least one computing cell array that may include a plurality of DRAM-based computing cells arranged in an array having at least one column in which the at least one column may include at least three rows of DRAM-based computing cells configured to provide a logic function that operates on a first row and a second row of the at least three rows and configured to store a result of the logic function in a third row of the at least three rows.

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: A memory module has a logic including a programming register, a deduplication ratio control logic, and a deduplication engine. The programming register stores a maximum deduplication ratio of the memory module. The control logic is configured to control a deduplication ratio of the memory module according to the maximum deduplication ratio. The deduplication ratio is programmable by the host computer.

Abstract: A system and method for using a Non-Volatile Dual In-Line Memory Module (NVDIMM) (110, 115) is disclosed. The NVDIMM (110, 115) can support two or more access modes. An application can specify which access mode is desired for an address space requested by the application. A Non-Volatile Memory (NVM) governor (150) can store an address mask and the access mode for the address space (305, 310, 315) in an NVM control register (155). When the application requests read or write access to an address (605), the NVM governor (150) can compare the requested address (605) with the address masks in the NVM control register (155), determine the access mode from the access mode corresponding to the matched address mask, and use that access mode to satisfy the request for the address (605).

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD can include a host interface logic, a data input buffer, a data output buffer, and a buffer manager to manage the data input buffer and data output buffer. A re-order logic can advise the buffer manager about which data should be returned to the host computer from the data output buffer.

Abstract: A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

Abstract: A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address bits, and addressed by a row command specifying a third number of row address bits followed by a column command specifying a fourth number of column address bits, the first number being greater than the third number or the second number being greater than the fourth number, includes: splitting the first number of row address bits into first and second subsets, and specifying the first subset in the row command and the second subset in a next address command when the first number is greater than the third number; otherwise splitting the second number of column address bits into third and fourth subsets, and specifying the fourth subset in the column command and the third subset in a previous address command.

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.