Abstract: An analog-to-digital converter includes an integrator, a single comparator, a successive approximation result register, and correction circuitry. The comparator is coupled to an output of the integrator. The successive approximation result register is coupled to an output of the comparator. The correction circuitry is configured to determine whether a sum of a reference voltage and an output voltage of the integrator changes an output of the comparator. The correction circuitry is also configured to, responsive to the sum of the reference voltage and the output of the integrator not changing the output of the comparator, add twice the reference voltage to the output of the integrator to produce a bit value at the output of the comparator, and select a bit value to be loaded into the successive approximation result register based on the bit value at the output of the comparator.

Abstract: An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Abstract: Devices, systems and methods are disclosed for assigning unique addresses to slave devices in a system comprising a host controller and multiple slave devices connected in a daisy chain configuration. The host controller initiates the address programming protocol, resulting in address assignment commands propagating along the daisy chain to each of the slave devices. Upon receiving an address assignment, each slave device issues an updated address assignment for the neighboring downstream slave device in the daisy chain. In this manner, slave devices are uniquely addressed using a single command, such that slave devices do not require factory-programmed device addresses. Also disclosed are communication protocols that allow the host controller to communicate with each of the daisy-chained slave devices or with certain subsets of the slave devices.

Abstract: An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Abstract: A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0×16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small VBE voltages on the second conductor. The relatively large and small VBE voltages provide differential band gap charges (QCA-QCB) which are averaged to provide a stable band gap reference voltage (VREF).

Abstract: Conventional “on-chip” or monolithically integrated thermocouples are very mechanically sensitive and are expensive to manufacture. Here, however, thermocouples are provided that employ different thicknesses of thermal insulators to help create thermal differentials within an integrated circuit. By using these thermal insulators, standard manufacturing processes can be used to lower cost, and the mechanical sensitivity of the thermocouple is greatly decreased. Additionally, other features (which can be included through the use of standard manufacturing processes) to help trap and dissipate heat appropriately.

Abstract: A method is provided. A communication is received by an input pin of an IC over a single-wire bus, where the communication includes a command byte. If the command byte is an initialization command byte, a self-addressing operation is performed to identify a bus address for the IC. Alternatively, if the command byte is a data movement command byte, a data movement operation is performed. When data movement operation is performed, the bus interface of the IC is set from the transparent mode to the operational mode if an operation address from the command byte matches the bus address so that a register identified in the command byte can be accessed and data movement with the register can be performed.

Abstract: A circuit for generating a band gap reference voltage (VREF) includes circuitry (I3×7) for supplying a first current to a first conductor (NODE1) and a second current to a second conductor (NODE2). The first conductor is successively coupled to a plurality of diodes (Q0×16), respectively, in response to a digital signal (CTL-VBE) to cause the first current to successively flow into selected diodes. The second conductor is coupled to collectors of the diodes which are not presently coupled to the first conductor. The diodes are successively coupled to the first conductor so that the first current causes the diodes, respectively, to produce relatively large VBE voltages on the first conductor and the second current causes sets of the diodes not coupled to the first conductor to produce relatively small VBE voltages on the second conductor. The relatively large and small VBE voltages provide differential band gap charges (QCA-QCB) which are averaged to provide a stable band gap reference voltage (VREF).

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: A programmable offset amplifier includes first (M1) and second (M2) input transistors having differentially connected sources and gates coupled to first (Vin+) and second (Vin?) input voltages. A tail current (Itail1) is shared between the first and second input transistors. First (M3) and second (M4) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage (13) has a first input (+) coupled to the drain of the second input transistor and a second input (?) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Abstract: An instrumentation amplifier includes first (11A) and second (12A) input amplifiers having outputs (15A,B) coupled to an output amplifier (13). A first auto-zero stage (20) in the first input amplifier is auto-zeroed to a first voltage level (VREFL), a first input signal (Vin+) is amplified by a second auto-zero stage (24) in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage (44) in the second input amplifier is auto-zeroed to a second voltage level (VREFH), a second input signal (Vin?) is amplified by a fourth auto-zero stage (40) in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (20), and the amplified first input signal is coupled to the output amplifier, during a third phase (C).

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: A differential amplifier includes a differential input pair (2A) coupled to a folded cascode stage (2B) and a common mode feedback circuit (34) including a tracking circuit (30A) coupled to first (Vout?) and second (Vout+) outputs of the folded cascode stage (2B). The first and second outputs are coupled to first terminals of first (31A) and second (31B) tracking capacitors which have second terminals on which a first common mode output signal (VCM1) is produced and also are coupled to first terminals of third (32A) and fourth (32B) tracking capacitors, respectively, which have second terminals on which a second common mode output signal (VCM2) is produced. The first and third tracking capacitors are discharged by first (27A) and second (27B) switches that directly couple the first and second outputs to first and second inputs of a common mode feedback amplifier (4). A desired common mode output voltage (VCM-IN) is applied to a third input of the common mode feedback amplifier.

Abstract: A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first amplifier (2) and an output chopper (10) for chopping an output signal of the first amplifier and applying it to the input of a switched capacitor notch filter (30-1).

Abstract: A chopper-stabilized amplifier (1B) having a first output (25) includes an input chopper (9) for chopping an input signal and applying it to the input of a first amplifier (2) and an output chopper (10) for chopping an output signal of the first amplifier and applying it to the input of a switched capacitor notch filter (30-1).

Abstract: A dual path chopper-stabilized amplifier (100) includes first (11) and second (11A) chopping/notch-filtering paths, each including an input chopper (9,9A), a transconductance amplifier (2,2A), and a notch filter (15,15A). Chopping and notch filtering in the first path are controlled by first (CHOPCLK) and second (FILTERCLK) clock signals, respectively. Chopping and notch filtering in the second path are controlled by the second (FILTERCLK) and first (CHOPCLK) clock signals, respectively. Outputs of the first (15) and second (15A) switched capacitor notch filters are combined to provide an amplifier output signal (23A,B) that updates a capacitance (C4) at 4 times the frequency of the filter clock signal, to thereby improve amplifier stability without increasing clock frequency.

Abstract: A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (?Vbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (?Vbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue?Vref or 2×Vresidue+Vref.