Abstract: A current sense amplifier includes a first amplifier stage, a second amplifier stage, a switch, and a common-mode transient detector. The first amplifier stage has a first amplifier output, a second amplifier output, a first amplifier input, and a second amplifier input. The second amplifier stage has a third amplifier input coupled to the first amplifier output, and a fourth amplifier input coupled to the second amplifier output. The switch has a switch control input, a first switch terminal coupled to the third amplifier input, and a second switch terminal coupled to the fourth amplifier input. The common-mode transient detector circuit has a detector output, a first detector input and a second detector input. The detector output is coupled to the switch control input. The first detector input is coupled to the first amplifier input. The second detector input is coupled to the second amplifier input.

Abstract: An example apparatus includes: a differential amplifier including: an inverting input coupled to a first input via a first resistor; a non-inverting input coupled to a second input via a second resistor; a first supply input coupled to the first input via a third resistor, and the first supply input coupled to the second input via a fourth resistor; a second supply input coupled to a current source; a non-inverting output; and an inverting output; a first transistor including a first control terminal and a first current terminal, the first control terminal coupled to the non-inverting output and the first current terminal coupled to the inverting input; and a second transistor including a second control terminal and a second current terminal, the second control terminal coupled to the inverting output and the second current terminal coupled to the non-inverting input.

Abstract: Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.

Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.

Abstract: A Hall effect sensor including a Hall element disposed at a surface of a semiconductor body, including a first doped region of a first conductivity type disposed over and abutted by an isolated second doped region of a second conductivity type. First through fourth terminals of the Hall element are in electrical contact with the first doped region, and a fifth terminal in electrical contact with the second doped region. A Hall effect sensor includes a first current source coupled to the first terminal of the Hall element, and common mode feedback regulation circuitry. The common mode feedback regulation circuitry has an output coupled to the third terminal and a ground node, and having an input coupled to the second and fourth terminals of the Hall element, and an output coupled to the third terminal and a ground node, where the second doped region is coupled to the third terminal.

Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

Abstract: A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

Abstract: A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.

Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Abstract: A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.

Abstract: A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.

Abstract: Embodiments relate to a circuit including a first circuit branch, a second circuit branch, and an integrator circuit. The first branch includes a first transistor and a first current source to generate a first CTAT voltage signal that includes components corresponding to parasitic base and emitter resistances of the first transistor. The second branch includes a second transistor and a second current source to generate a second CTAT voltage signal that includes components corresponding to parasitic base and emitter resistances of the second transistor. The first and second circuit branches are coupled to the integrator circuit such that the integrator circuit integrates a difference between the first and second CTAT voltage signals such that the integrated signal does not include any components corresponding to parasitic base and emitter resistances.

Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Abstract: A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.

Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.

Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.

Abstract: Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.

Abstract: In some examples, a level shifter circuit comprises: a first transistor pair cascoded at a first input node; a second transistor pair cascoded at a second input node, wherein the first and transistor pairs couple at a first node, a second node, a third node, and a fourth node; a third transistor pair coupled to the first transistor pair at the first and the third nodes, wherein the third transistor pair is configured to generate a first bipolar clock signal; a fourth transistor pair coupled to the second transistor pair at the second and the fourth nodes, wherein the fourth transistor pair is configured to generate a second bipolar clock signal; and a clock generation circuit coupled to the first node, the second node, the third node, and the fourth node.