Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract: A content addressable memory (CAM) row is disclosed. The CAM row includes one or more compare circuits coupled between a match line and a virtual-ground line. The compare circuits are configured to compare a search key with CAM cell data words. The CAM row also includes a pre-charge circuit controlled by a pre-charge signal, and includes a tank capacitor. The pre-charge circuit is configured to pre-charge the match line to a supply voltage in response to assertion of the pre-charge signal. A pull-down transistor dynamically discharges the virtual-ground line to ground potential.

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract: Systems, methods, and circuits provide phase inversion of a clock signal. A first clock signal is received. A phase inversion signal indicates the existence of a 180 degree phase difference between the first clock signal and a second clock signal. As a result of the phase inversion signal indicating the 180 degree phase difference, the system, methods and circuits adapt the first clock signal by extending the first clock signal by a phase such that the first clock signal's rising edges and falling edges align with the second clock signal's rising edges and falling edges. As a result, the 180 degree phase difference between the clock signals is eliminated.

Abstract: A CAM cell is disclosed that can be selectively configured to store either base-2 data words or base-3 data words. When configured to store base-3 data words, the quaternary CAM cell compares 3 comparand bits representative of a base-3 comparand value with the base-3 data value stored in the CAM cell. Storing base-3 data words in such CAM cells increases the data storage density of associated CAM arrays.

Abstract: Quaternary CAM cells are provided that include a compare circuit having a discharge path between a match line and ground potential, the single discharge path consisting essentially of a single transistor. In an embodiment, the single transistor has a gate coupled to a pull-down node and the compare circuit includes first and second gating transistors connected in series between the pull-down node and a ground potential, the first gating transistor having a gate to receive a comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.

Abstract: A CAM device for comparing a search key with a plurality of ternary words stored in a CAM array includes one or more population counters, a pre-compare memory, and a pre-compare circuit. The present embodiments reduce the power consumption of CAM devices during compare operations between a search key and ternary words stored in a CAM array by selectively enabling the match lines in the CAM array in response to pre-compare operations between a set of population counts corresponding to the masked search key and a set of population counts corresponding to the ternary words stored in the CAM array.

Abstract: Ternary CAM cells are disclosed that include a compare circuit that includes a discharge path having a single pull-down transistor coupled between the match line and ground potential.

Abstract: Ternary CAM cells include a compare circuit including a discharge path having only two pull-down transistors coupled between the match line and ground potential.

Abstract: A CAM array includes a plurality of regular rows and a reference row. Each regular row is partitioned into a plurality of row segments, with each row segment including a number of CAM cells coupled to a corresponding match line segment. The reference row generates self-timed control signals for corresponding segments of the regular rows. Control circuits selectively enable a respective row segment in response to a logical combination of match results in a previous row segment and an associated one of the self-timed control signals.

Abstract: Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, with each parallel path consisting of a single pull-down transistor having a gate selectively coupled to the stored data value in response to a comparand value.

Abstract: Power consumption of CAM devices is reduced during compare operations between a search key and data stored in the device's array by reducing the amount of electric charge by which the match line is discharged during mismatch conditions. More specifically, for some embodiments, each row of the CAM array includes circuitry that discharges the match line to a virtual ground node rather than to ground potential during mismatch conditions. Because the electrical potential on the virtual ground node is greater than ground potential, power consumption associated with charging the match line back to a logic high state during the next compare operation is reduced.

Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.

Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.

Abstract: An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes a number of MLR cells and includes a parity circuit having a number of inputs coupled to the outputs of the MLR cells and having an output to generate a corresponding bit of the revision code. The MLR cells in each MLR group structure are assigned to different device layers, and each device layer is assigned to one MLR cell in each MLR group structure. Each revision code bit is controllable by any MLR cell in the corresponding MLR group structure.

Abstract: A CAM device for comparing a search key with a plurality of CAM words stored in a main CAM array includes a pre-compare CAM array and match line control logic. The pre-compare CAM array includes a plurality of rows, each for storing a set of pre-compare bits generated by performing a logical function on a corresponding CAM word. The match line control logic selectively pre-charges match lines in the main CAM array in response to match results from a pre-compare operation between an encoded search key and corresponding sets of pre-compare bits.

Abstract: A method, and a corresponding data structure, are used for designing a circuit by displaying signal information on a schematic diagram of the circuit to aid in resolving design problems. A circuit design is stored as data in a computer memory. An E-CAD tool software application is performed on the design to create an archive file containing x-y display coordinates for displaying the signals as part of a schematic. The archive file contains names and locations of all signals. The design is analyzed to extract signal information. Timing information may be extracted using a timing analyzer. The information is stored in a data file, such as a timing data file in the computer memory. Timing information and signal display coordinate information may be combined into a new archive file that is used to create a schematic diagram of the circuit, or a portion of the circuit, in which the timing information is displayed near the signals and signal names.

Abstract: A method, and a corresponding data structure, are used for designing a circuit by displaying signal information on a schematic diagram of the circuit to aid in resolving design problems. A circuit design is stored as data in a computer memory. An E-CAD tool software application is performed on the design to create an archive file containing x-y display coordinates for displaying the signals as part of a schematic. The archive file contains names and locations of all signals. The design is analyzed to extract signal information. Timing information may be extracted using a timing analyzer. The information is stored in a data file, such as a timing data file in the computer memory. Timing information and signal display coordinate information may be combined into a new archive file that is used to create a schematic diagram of the circuit, or a portion of the circuit, in which the timing information is displayed near the signals and signal names.