Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.

Abstract: One illustrative device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in the layer of insulating material and a bi-layer cap layer comprised of a first layer of material positioned on the copper-based conductive structure and a second layer of material positioned on the first layer of material. One method disclosed herein includes forming a copper-based conductive structure in a first layer of insulating material, forming a first layer of a bi-layer cap layer on the copper-based conductive structure, the first layer being comprised of silicon carbon nitride, forming a second layer of the bi-layer cap layer on the first layer, the second layer being comprised of silicon nitride, and forming a second layer of insulating material above the second layer.

Abstract: A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.