Abstract: A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode.

Abstract: A nanowire field effect junction diode constructed on an insulating transparent substrate that allows form(s) of radiation such as visual light, ultraviolet radiation; or infrared radiation to pass. A nanowire is disposed on the insulating transparent substrate. An anode is connected to a first end of the nanowire and a cathode is connected to the second end of the nanowire. An oxide layer covers the nanowire. A first conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the anode. A second conducting gate is disposed on top of the oxide layer adjacent with a non-zero separation to the cathode and adjacent with a non-zero separation the first conducting gate. A controllable PN junction may be dynamically formed along the nanowire channel by applying opposite gate voltages. Radiation striking the nanowire through the substrate creates a current the anode and cathode.

Abstract: Disclosed is a Silicon-On-Insulator (SOI) Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) logic family composed of ratioed logic with intrinsically “on” symmetric fully depleted double-gate (DG) SOI MOSFET load(s) and asymmetric fully depleted double gate MOSFET driver(s).

Abstract: A simple stacked gate Electrically Erasable Programmable Read Only Memory (EEPROM) device fabricated on Silicon-on-Insulator (SOI) substrates(films) and a method to erase data in such device as well as in any other EEPROM devices fabricated on SOI substrates(films) is described. The new EEPROM device incorporates two separate control gates, a front control gate and a back control gate. In the new erasing method the back control gate is used to operate back channel of the EEPROM device in the avalanche region and generate hot carriers subsequently injected into the floating gate. The new erasing method is applicable to either n-channel or p-channel, inversion, accumulation or depletion mode devices.