Abstract: Methods for routing in the design of integrated circuits (ICs) to simplify the routing task. The method includes dividing a given IC design into a limited number of non-overlapping tiles, and then routing all tiles in parallel, each tile being independently routed by a standard router. Thereafter, routed tiles are assembled to form a routing solution for the entire IC. Details of exemplary methods are disclosed.

Abstract: A system for performing parallel distributed processing thereby accelerating the generation of a physical layout is disclosed. Specifically, the system significantly reduces the execution time of a place and route stage in the design of an integrated circuit (IC). An IC design is broken to multiple tiles that are independently processed and routed in parallel. This is achieved by providing an infrastructure that manages the multi-processing as well as data flows between a main computing node and a plurality of remote processing nodes.

Abstract: A STANDARD BLOCK architecture for integrated circuit (IC) design. The STANDARD BLOCK architecture provides a new level of abstraction with a granularity and regularity that is most appropriate for the physical implementation of complex, large scale deep-submicron IC designs. To this end, the STANDARD BLOCK architecture combines the advantages of standard-cell-based and functional-block-based architectures. The STANDARD BLOCK architecture includes a STANDARD BLOCK form that is physically constrained having one fixed or quantized dimension and one variable dimension that ranges between predefined limits. The STANDARD BLOCK granularity is larger than the standard cell granularity such that each STANDARD BLOCK includes a plurality of standard cells. In the STANDARD BLOCK architecture, each STANDARD BLOCK has flexible physical design properties.

Abstract: An integrated circuit (IC) architecture with STANDARD BLOCKs. The IC architecture forms a layout that includes a plurality of STANDARD BLOCKs, top-level cells, and hard IP blocks. The STANDARD BLOCKS form row-based or column-based STANDARD BLOCK ARRAY configurations in which STANDARD BLOCKs are placed adjacent to each other in a row or column configuration with their fixed or quantized dimension aligned and oriented perpendicular to the STANDARD BLOCK ARRAY direction. Individual STANDARD BLOCK ARRAYs can be spaced apart forming channels between them to allow for routing interconnections, or overlapping one another in a flipped configuration sharing VDD or GND power rails. The IC layout includes sites reserved for top-level cells that are placed in channels between STANDARD BLOCK ARRAYs, around the perimeter of STANDARD BLOCKs, or arranged in a staggered or diagonal configuration inside the STANDARD BLOCKs.