Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.

Abstract: A voltage proportional to a sum of currents flowing though first and second coupled inductors is developed across a first capacitor common to first and second series RC networks if the RC networks are time constant-matched to the inductors. The first and second inductors are coupled between a first and second switched drive phase input terminal, respectively, and an apparatus output terminal. The first and second RC networks are coupled in parallel with the first and second inductor, respectively. Inverting and non-inverting inputs of an amplifier are coupled to junctions of third and fourth time constant-matched series RC networks coupled in parallel with the first and second inductors, respectively. The amplifier subtracts voltages sensed at the junctions to generate a difference signal proportional to a magnitude difference of the currents flowing through the inductors.

Abstract: An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.

Abstract: A voltage proportional to a sum of currents flowing though first and second coupled inductors is developed across a first capacitor common to first and second series RC networks if the RC networks are time constant-matched to the inductors. The first and second inductors are coupled between a first and second switched drive phase input terminal, respectively, and an apparatus output terminal. The first and second RC networks are coupled in parallel with the first and second inductor, respectively. Inverting and non-inverting inputs of an amplifier are coupled to junctions of third and fourth time constant-matched series RC networks coupled in parallel with the first and second inductors, respectively. The amplifier subtracts voltages sensed at the junctions to generate a difference signal proportional to a magnitude difference of the currents flowing through the inductors.

Abstract: An amplifier receives a differential signal and, in response, generates a first negative input current and a first positive input current. In a first operating mode, the amplifier receives a second differential signal, and, in response, generates a second negative input current and a second positive input current. In a second operating mode, the amplifier receives the second differential signal, and, in response, generates a third negative input current and a third positive input current. When the device is operating in the first operating mode, the first negative input current is summed with the second negative input current and the first positive input current is summed with the second positive input current. When the device is operating in the second operating mode, the first negative input current is summed with the third negative input current and the first positive input current is summed with the third positive input current.

Abstract: An integrated circuit chip and method for EEG monitoring. In one embodiment, the integrated circuit chip includes an Analog Front End cell in communication with an electrode and a Classification Processor wherein a signal received from the electrode is processed by the Classification Engine cell and designated as seizure or non-seizure. In another embodiment, the Analog Front End cell includes an amplifier cell in communication with an electrode; and an ASPU cell in communication with the amplifier cell. In yet another embodiment, the Classification Processor includes a DBE Channel Controller cell; a Feature Extraction Engine Processor cell, and a Classification Engine cell in communication with the Feature Extraction Engine Processor cells and the DBE Channel Controller cell.