Abstract: A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.

Abstract: A clock detector includes a first detector circuit, a second detector circuit, and a toggle detector circuit. The first detector circuit is for activating a first detect signal in response to detecting that a clock signal that toggles between first and second logic states when present is stuck in the first logic state, and keeping the first detect signal inactive otherwise. The second detector circuit is for providing a second detect signal in response to detecting that the clock signal is stuck in the second logic state, and keeping the second detect signal inactive otherwise. The toggle detector circuit is for activating a toggle detect signal in response to both the first detect signal and the second detect signal being inactive, and keeping the toggle detect signal inactive in response to an activation of either the first detect signal or the second detect signal.

Abstract: A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a

Abstract: A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a