Patents by Inventor Dinesh A. Mehta

Dinesh A. Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4216489
    Abstract: In a dynamic MOS (Metal Oxide Semiconductor) random access memory, reverse bias leakage currents which deplete stored charges are reduced by minimizing minority carrier generation-type currents. By so minimizing these currents, the leakage currents become dominated by minority carrier diffusion currents. The memory is ideally formed in an upper semiconductor layer (14) of a layered structure (11). The semiconductor layer (14) is grown epitaxially with a relatively low dopant concentration on a semiconductor substrate (12) with a dopant concentration of the same conductivity type and about three orders of magnitude greater than that of the epitaxially grown layer. The epitaxially grown structure is advantageously suited for the memory circuits in that it may be formed with very low leakage currents. The material further offers by its layered structure a basis for optimizing dynamic memory device characteristics.
    Type: Grant
    Filed: January 22, 1979
    Date of Patent: August 5, 1980
    Assignees: Bell Telephone Laboratories, Incorporated, Western Electric Co., Inc.
    Inventors: James T. Clemens, Dinesh A. Mehta, James T. Nelson, Charles W. Pearce, Robert C. Sun