Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: A technique for the removal of a retained ureteral stent involves attaching a proximal end of the stent to a pulling member and pulling the proximal end of the stent through a lumen of an elongate device using the pulling member so that a distal end of the device advances along the stent up the ureter towards a blockage retaining the stent. As such, pressure applied by the distal end of the device in opposition to the stent pulled in respective tension removes the blockage.

Abstract: Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.

Abstract: A device may receive document image data that includes an image of a document to be digitized. The device may detect, from the document image data, a table of information that is depicted in the image. The device may determine a data extraction score associated with a table image, wherein the data extraction score is associated with using a data conversion technique to convert the table image to digitized table data. The device may perform, based on the data extraction score not satisfying a threshold, a morphological operation on the table image to generate an enhanced table image that corresponds to an enhanced table of information associated with the table of information. The device may process, using the data conversion technique, the enhanced table image to extract the information from the enhanced table. The device may perform an action associated with the extracted information.

Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.

Abstract: A device may receive document image data that includes an image of a document to be digitized. The device may detect, from the document image data, a table of information that is depicted in the image. The device may determine a data extraction score associated with a table image, wherein the data extraction score is associated with using a data conversion technique to convert the table image to digitized table data. The device may perform, based on the data extraction score not satisfying a threshold, a morphological operation on the table image to generate an enhanced table image that corresponds to an enhanced table of information associated with the table of information. The device may process, using the data conversion technique, the enhanced table image to extract the information from the enhanced table. The device may perform an action associated with the extracted information.

Abstract: A device may receive document image data that includes an image of a document to be digitized. The device may detect, from the document image data, a table of information that is depicted in the image. The device may determine a data extraction score associated with a table image, wherein the data extraction score is associated with using a data conversion technique to convert the table image to digitized table data. The device may perform, based on the data extraction score not satisfying a threshold, a morphological operation on the table image to generate an enhanced table image that corresponds to an enhanced table of information associated with the table of information. The device may process, using the data conversion technique, the enhanced table image to extract the information from the enhanced table. The device may perform an action associated with the extracted information.

Abstract: A device may receive document image data that includes an image of a document to be digitized. The device may detect, from the document image data, a table of information that is depicted in the image. The device may determine a data extraction score associated with a table image, wherein the data extraction score is associated with using a data conversion technique to convert the table image to digitized table data. The device may perform, based on the data extraction score not satisfying a threshold, a morphological operation on the table image to generate an enhanced table image that corresponds to an enhanced table of information associated with the table of information. The device may process, using the data conversion technique, the enhanced table image to extract the information from the enhanced table. The device may perform an action associated with the extracted information.

Abstract: The present disclosure includes methods and apparatus for executing a single binary code version of an application including an application identifier, transmitting a variable value request including the requestor identifier and the application identifier via an application programming interface to a portal, the variable value request requesting variable value information relating to the variable of the application associated with the requestor identifier, receiving a variable value response including the variable value information relating to the variable associated with the requestor identifier, wherein the variable value information identifies one of the first variable value or the second variable value, executing the first set of code to provide the first experience within the application based on the variable value information identifying the first variable value, and executing the second set of code to provide the second experience within the application based on the variable value information identifyi

Abstract: A non-volatile memory system accepts Secure Digital (SD) Commands and manages a data buffer that buffers data for the SD commands. The SD Commands may be accepted over an SD bus of the non-volatile memory system. The SD Commands may be accepted over a PCIe bus of the non-volatile memory system. The memory system may generate one or more NVMe commands for each SD command, and submit the NVMe command(s) to an NVMe submission queue. Upon completion all of the NVMe commands that were generated for an SD command, the memory system may report completion status of the SD command to an SD host. The memory system ensures that the timing requirements for SD commands are met even though a conversion from SD commands to NVMe commands may be performed. The memory system makes efficient use of the depth of the NVMe submission queue.

Abstract: Apparatus and method for performing wear leveling are disclosed. An ordered list of references to each of a set of memory blocks is stored. A set of memory blocks in the ordered list is sequentially allocating. The allocated set of memory blocks in the ordered list are erased in the sequence in which they were allocated.

Abstract: The present disclosure includes methods and apparatus for executing a single binary code version of an application including an application identifier, transmitting a variable value request including the requestor identifier and the application identifier via an application programming interface to a portal, the variable value request requesting variable value information relating to the variable of the application associated with the requestor identifier, receiving a variable value response including the variable value information relating to the variable associated with the requestor identifier, wherein the variable value information identifies one of the first variable value or the second variable value, executing the first set of code to provide the first experience within the application based on the variable value information identifying the first variable value, and executing the second set of code to provide the second experience within the application based on the variable value information identifyi

Abstract: A non-volatile memory system accepts Secure Digital (SD) Commands and manages a data buffer that buffers data for the SD commands. The SD Commands may be accepted over an SD bus of the non-volatile memory system. The SD Commands may be accepted over a PCIe bus of the non-volatile memory system. The memory system may generate one or more NVMe commands for each SD command, and submit the NVMe command(s) to an NVMe submission queue. Upon completion all of the NVMe commands that were generated for an SD command, the memory system may report completion status of the SD command to an SD host. The memory system ensures that the timing requirements for SD commands are met even though a conversion from SD commands to NVMe commands may be performed. The memory system makes efficient use of the depth of the NVMe submission queue.

Abstract: One or more control circuits of a storage system are configured to intelligently set a task readiness indicator for tasks on a task command queue. A memory controller may divide each of the tasks into one or more chunks. The memory controller initiates processing of at least some of the chunks for at least two tasks and determines a task readiness factor each of the tasks based on how far respective chunks have progressed in the processing. The memory controller sets a ready indicator in a task status register for a selected task based on the task readiness factor of the tasks. Therefore, task latency may be reduced. In one aspect, the memory controller allocates a ring buffer to chunks of an executing task. This ring buffer may assure that there will always be memory for the chunks of the task.

Abstract: One or more control circuits of a storage system are configured to intelligently set a task readiness indicator for tasks on a task command queue. A memory controller may divide each of the tasks into one or more chunks. The memory controller initiates processing of at least some of the chunks for at least two tasks and determines a task readiness factor each of the tasks based on how far respective chunks have progressed in the processing. The memory controller sets a ready indicator in a task status register for a selected task based on the task readiness factor of the tasks. Therefore, task latency may be reduced. In one aspect, the memory controller allocates a ring buffer to chunks of an executing task. This ring buffer may assure that there will always be memory for the chunks of the task.

Abstract: Technology is described herein for caching residual data in latches during a write operation of non-volatile storage. When writing data at the request of a host, it is possible for there to be some residual data that cannot be programmed at two (or more) bits per memory cell into a page of memory cells, given the programming scheme being used. This residual data may be cached in latches. The residual data from the latches may be combined with other data from the host to increase programming speed when programming, for example, sequential data using a full sequence programming scheme. Also, caching the residual data in latches keeps write amplification low.

Abstract: Disclosed are various embodiments for a high-performance computing framework for cloud computing environments. A parallel computing application executable by at least one computing device of the cloud computing environment can call a message passing interface (MPI) to cause a first one of a plurality of virtual machines (VMs) of a cloud computing environment to store a message in a queue storage of the cloud computing environment, wherein a second one of the plurality of virtual machines (VMs) is configured to poll the queue storage of the cloud computing environment to access the message and perform a processing of data associated with the message. The parallel computing application can call the message passing interface (MPI) to access a result of the processing of the data from the queue storage, the result of the processing being placed in the queue storage by the second one of the plurality of virtual machines (VMs).