Abstract: Embodiments herein describe a network on chip (NoC) that implements multi-path routing (MPR) between an ingress logic block and an egress logic block. The multiple paths between the ingress and egress logic blocks can be assigned different alias destination IDs corresponding to the same destination ID. The NoC can use the alias destination IDs to route the packets along the different paths through interconnected switches in the NoC.

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

Abstract: Implementing a circuit design using time-division multiplexing (TDM) can include determining a net signature for each of a plurality of nets of a circuit design. For each net, the net signature specifies location information for a driver and one or more loads of the net. The plurality of nets having a same net signature can be grouped according to distance between drivers of the respective nets. One or more subgroups can be generated based on a TDM ratio for each group. For one or more of the subgroups, a TDM transmitter circuit is connected to a TDM receiver circuit through a selected interconnect, the drivers of the nets of the subgroup are connected to the TDM transmitter circuit, and loads of the nets of the subgroup are connected to the TDM receiver circuit.

Abstract: A method includes receiving a value and an identifier from a first memory and hashing the identifier to produce a memory block identifier. The method also includes routing, based on the memory block identifier, a read request to a memory block of a plurality of memory blocks and updating the value received from the first memory based on a property received from the memory block in response to the read request. The memory further includes storing the updated value in the first memory.

Abstract: A method of FPGA compilation for an emulation system includes receiving a netlist for an FPGA, partitioning the netlist into a set of sub-FPGA netlists, and mapping each of the sub-FPGA netlists in the set to a corresponding dynamic sub-FPGA region of the FPGA. The method further includes implementing the sub-FPGA netlists of the set in parallel to obtain a corresponding set of sub-FPGA bitstreams.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: A circuit design tool places a circuit design, and after placing detects a hold violation of a path between a first flip-flop on a first IC die and a second flip-flop on a second IC die. The circuit design tool selects a window size based on an amount of the hold violation and determines an alternative path having a delay that resolves the hold violation. The alternative path is restricted to resources within an area of the window size on the second IC die. The circuit design tool replicates a plurality of instances of the alternative path in a plurality of areas of the second IC die and then routes the circuit design using the plurality of instances of the alternative path.

Abstract: Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.

Abstract: Method and system relate generally to generating a physical design for a circuit design. In such a method, a logical network is obtained from a logical netlist for the circuit design. A physical network for an integrated circuit chip is obtained. The physical network is converted into a routing graph. The logical network and the routing graph are combined to build an extended network. Routing is performed on the extended network for the logical netlist to perform placement and the routing concurrently to provide the physical design.

Abstract: Implementing a circuit design can include generating an integer linear programming (ILP) formulation for a routing problem by determining constraints for implementing nets of a circuit design within a programmable network-on-chip (NOC) of an integrated circuit, wherein the constraints include placement constraints and routability constraints for the nets. The nets can be simultaneously placed and routed by executing an ILP solver using a processor to minimize an objective function of the ILP formulation while observing the constraints. The ILP solver maps logical units of the nets to interface circuits of the programmable NOC concurrently with mapping the nets to channels of the programmable NOC.

Abstract: An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Abstract: A netlist of a circuit design includes an interface portion and a main portion. The interface portion is decomposed into multiple levels. Each level specifies connections between a respective first set of circuit elements and a respective second set of circuit elements. The second set of circuit elements in each level, except a last level, includes the first set of circuit elements in a next level. The first set of circuit elements identified in a first level of the multiple levels have fixed locations. The second set of circuit elements in the multiple levels is placed-and-routed. The placing-and-routing of the second set of circuit elements in one level is completed before commencing placing-and-routing of the second set of circuit elements in the next level. The main portion is placed-and-routed after placing-and-routing the second set of circuit elements in the multiple levels.

Abstract: Re-budgeting connections includes detecting a budget event for a circuit design and, responsive to detecting the budget event, calculating, using a processor, a delta for a selected combinatorial circuit element of the circuit design using an incoming slack and an outgoing slack of the selected combinatorial circuit element. Using the processor, a delay budget for a connection of the selected combinatorial circuit element is adjusted using the delta responsive to detecting the budget event.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: A computer-implemented method of converting a circuit design for a programmable logic device (PLD) to a standard cell circuit design can include unmapping a PLD circuit design to a gate level netlist, mapping logic gates of the netlist to functionally equivalent standard cells, and including the standard cells within the standard cell circuit design. Design constraints for the standard cell circuit design can be automatically generated. The design constraints for the standard cell circuit design can be output.

Abstract: A method performed by a system comprising a processor and a memory can include performing a global placement of a circuit design for a target programmable integrated circuit (IC) and clustering the circuit design using a selected size of cluster regions according to control sets identified within the circuit design. The method further can include determining a legalized placement of the clustered circuit design by solving a minimum cost network flow problem for the selected size of the cluster regions and the target programmable IC and assigning components to sites of the target programmable IC according to the legalized placement. The circuit design specifying the legalized placement can be stored within the memory.

Abstract: Various approaches for improving clock speed for a circuit design. In one embodiment, a graph having nodes and edges that represent the circuit design is generated. The nodes represent flip-flops of the design, the edges represent couplings of data inputs and outputs of the flip-flops, and the edges have associated delay values for respective durations of signal delays of the couplings. A smallest period is determined for which subtracting each delay value from the smallest period and associating the difference with the associated edge does not create a negative cycle in the graph. A path in the graph is selected, the path including selected flip-flops and connecting edges. The circuit design is modified by replacing the selected flip-flops with latches, and the smallest period is output.

Abstract: Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.

Abstract: A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for each of a plurality of banks of the IC, determining a cost of assigning the selected bus to the bank according, at least in part, to a measure of proximity of the bank to another bank including a bus of the interface. The method can include selecting an available bank having a lowest cost, assigning at least one of the plurality of I/O pins of the selected bus not assigned to a bank of the IC to the selected bank, and outputting a circuit design including an association of I/O pin(s) of the selected bus to the selected bank.