Patents by Inventor Dinesh D. Patil
Dinesh D. Patil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230305982Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: May 31, 2023Publication date: September 28, 2023Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11693810Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 24, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20220121595Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 24, 2021Publication date: April 21, 2022Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11237998Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 22, 2020Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 11100029Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: August 8, 2019Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20210109883Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jacob Raymond Jones
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Publication number: 20190361831Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 10445278Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: GrantFiled: December 28, 2016Date of Patent: October 15, 2019Assignee: Intel CorporationInventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Publication number: 20180181524Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Jeffrey Erik Schulz, David W. Mendel, Dinesh D. Patil, Gary Brian Wallichs, Keith Duwel, Jakob Raymond Jones
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Patent number: 8964879Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.Type: GrantFiled: July 9, 2013Date of Patent: February 24, 2015Assignee: Rambus Inc.Inventors: Reza Navid, Amir Amirkhany, Dinesh D. Patil, Brian S. Leibowitz
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Publication number: 20140023161Abstract: Data coding schemes perform level-based and/or transition-based encoding to avoid signaling conditions that create worst case crosstalk during transmission of multi-bit data from one circuit to another circuit via a parallel communication link. The coding schemes disallow certain patterns from being present in the signal levels, signal transitions, or a combination of the signal levels and signal transitions that occur in a subset of the multi-bit data that corresponds to certain physically neighboring wires of the parallel communication link.Type: ApplicationFiled: July 9, 2013Publication date: January 23, 2014Inventors: Reza Navid, Amir Amirkhany, Dinesh D. Patil, Brian S. Leibowitz
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Patent number: 8599468Abstract: An optical device that includes a wavelength-sensitive optical component, which has an associated thermal time constant, is described. Note that an operating wavelength of the wavelength-sensitive optical component is a function of several physical parameters including temperature. Moreover, the optical device includes a heating mechanism that provides heat to the wavelength-sensitive optical component. Furthermore, the optical device includes a driver circuit that provides a pulse-width modulated signal to the heating mechanism. Note that an average pulse-width modulated heat provided by the heating mechanism, and which corresponds to the pulse-width modulated signal, thermally tunes the wavelength-sensitive optical component to a target operating wavelength. Additionally, note that the target operating wavelength corresponds to a target operating temperature of the wavelength-sensitive optical component.Type: GrantFiled: August 9, 2011Date of Patent: December 3, 2013Assignee: Oracle International CorporationInventors: Frankie Y. Liu, Dinesh D. Patil, Ronald Ho, Ashok V. Krishnamoorthy
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Patent number: 8582985Abstract: An optical receiver is described. This optical receiver has two operating modes: a calibration mode and a normal mode. During the normal mode, switches are used to electrically couple an input of a transimpedance amplifier (TIA) to an optical-to-electrical (OE) converter that receives an optical signal and provides a corresponding analog electrical signal. Moreover, during the calibration mode, the switches are used to electrically isolate the input of the TIA from the OE converter while maintaining a feedback path from an output of the TIA to the input of the TIA, thereby ensuring proper bias of the TIA during calibration. Furthermore, a frequency response of the TIA during the normal mode is substantially unchanged over an operating bandwidth of the TIA by the capability to electrically isolate the input of the TIA from the OE converter during the calibration mode.Type: GrantFiled: June 9, 2011Date of Patent: November 12, 2013Assignee: Oracle International CorporationInventors: Frankie Y. Liu, Dinesh D. Patil
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Publication number: 20130038920Abstract: An optical device that includes a wavelength-sensitive optical component, which has an associated thermal time constant, is described. Note that an operating wavelength of the wavelength-sensitive optical component is a function of several physical parameters including temperature. Moreover, the optical device includes a heating mechanism that provides heat to the wavelength-sensitive optical component. Furthermore, the optical device includes a driver circuit that provides a pulse-width modulated signal to the heating mechanism. Note that an average pulse-width modulated heat provided by the heating mechanism, and which corresponds to the pulse-width modulated signal, thermally tunes the wavelength-sensitive optical component to a target operating wavelength. Additionally, note that the target operating wavelength corresponds to a target operating temperature of the wavelength-sensitive optical component.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Frankie Y. Liu, Dinesh D. Patil, Ronald Ho, Ashok V. Krishnamoorthy
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Publication number: 20120315052Abstract: An optical receiver is described. This optical receiver has two operating modes: a calibration mode and a normal mode. During the normal mode, switches are used to electrically couple an input of a transimpedance amplifier (TIA) to an optical-to-electrical (OE) converter that receives an optical signal and provides a corresponding analog electrical signal. Moreover, during the calibration mode, the switches are used to electrically isolate the input of the TIA from the OE converter while maintaining a feedback path from an output of the TIA to the input of the TIA, thereby ensuring proper bias of the TIA during calibration. Furthermore, a frequency response of the TIA during the normal mode is substantially unchanged over an operating bandwidth of the TIA by the capability to electrically isolate the input of the TIA from the OE converter during the calibration mode.Type: ApplicationFiled: June 9, 2011Publication date: December 13, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Frankie Y. Liu, Dinesh D. Patil
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Patent number: 8238761Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.Type: GrantFiled: December 9, 2009Date of Patent: August 7, 2012Assignee: Oracle America, Inc.Inventors: Frankie Y. Liu, Dinesh D. Patil, Ronald Ho, Elad Alon
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Patent number: 8155538Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.Type: GrantFiled: December 9, 2009Date of Patent: April 10, 2012Assignee: Oracle America, Inc.Inventors: Philip Amberg, Dinesh D. Patil, Frankie Y. Liu
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Publication number: 20110135320Abstract: A technique for calibrating an optical receiver is described. During this technique, a front-end circuit in the optical receiver receives an optical signal that corresponds to a sequence with alternating groups of symbol types that correspond to binary values, where durations of the groups of a given symbol type, which can correspond to a first binary value or a second binary value, progressively decrease during the sequence. Then, the output of the feedback circuit is adjusted based at least on the sequence. When the durations of groups corresponding to the first binary value and the second binary value reach their minimum values in the sequence, a calibration value corresponding to the output of the feedback circuit is stored for use during a normal operating mode of the optical receiver.Type: ApplicationFiled: December 9, 2009Publication date: June 9, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Philip Amberg, Dinesh D. Patil, Frankie Y. Liu
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Publication number: 20110135315Abstract: An optical receiver is described. This optical receiver includes a digital feedback circuit that biases a front-end circuit, which receives an optical signal, so that an analog electrical signal output by the front-end circuit is calibrated relative to a reference voltage corresponding to a decision threshold of a digital slicer in the optical receiver. In particular, during a calibration mode the feedback circuit may determine and store a calibration value that calibrates the analog electrical signal relative to the reference voltage. Then, during a normal operating mode, the feedback circuit may output a current corresponding to the stored calibration value that specifies a bias point of the front-end circuit.Type: ApplicationFiled: December 9, 2009Publication date: June 9, 2011Applicant: SUN MICROSYSTEMS, INC.Inventors: Frankie Y. Liu, Dinesh D. Patil, Ronald Ho, Elad Alon