Patents by Inventor Dinesh J. Alladi
Dinesh J. Alladi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9645591Abstract: Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.Type: GrantFiled: January 9, 2014Date of Patent: May 9, 2017Assignee: QUALCOMM IncorporatedInventors: Masoud Roham, Wei Zheng, Liang Dai, Dinesh J. Alladi, Yuhua Guo
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Patent number: 9197198Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.Type: GrantFiled: October 29, 2013Date of Patent: November 24, 2015Assignee: QUALCOMM IncorporatedInventors: Omid Rajaee, Dinesh J Alladi
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Publication number: 20150192943Abstract: Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.Type: ApplicationFiled: January 9, 2014Publication date: July 9, 2015Applicant: QUALCOMM IncorporatedInventors: Masoud ROHAM, Wei ZHENG, Liang DAI, Dinesh J. ALLADI, Yuhua GUO
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Publication number: 20150116020Abstract: The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.Type: ApplicationFiled: October 29, 2013Publication date: April 30, 2015Applicant: QUALCOMM IncorporatedInventors: Omid Rajaee, Dinesh J. Alladi
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Patent number: 8994568Abstract: A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.Type: GrantFiled: March 1, 2013Date of Patent: March 31, 2015Assignee: QUALCOMM IncorporatedInventors: Karthik Nagarajan, Dinesh J Alladi
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Publication number: 20140253210Abstract: Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.Type: ApplicationFiled: March 6, 2013Publication date: September 11, 2014Applicant: QUALCOMM INCORPORATEDInventors: Omid Rajaee, Wei Zheng, Dinesh J. Alladi, Yuhua Guo
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Publication number: 20140247170Abstract: A method and apparatus for controlling supply voltage for a successive approximation register analog to digital converter and comparator common mode voltage. The method comprises: measuring a successive approximation register conversion time; comparing the successive approximation register conversion time with a desired conversion time; and if necessary, performing a closed loop adjustment of at least one of the supply and/or comparator common mode voltage. The apparatus consists of a common mode voltage and regulator correction module. The common mode voltage and regulator correction module includes a phase frequency detector, a charge pump and may include a transconductance cell.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: QUALCOMM IncorporatedInventors: Karthik Nagarajan, Dinesh J. Alladi
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Patent number: 8564346Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).Type: GrantFiled: January 23, 2012Date of Patent: October 22, 2013Assignee: QUALCOMM IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Publication number: 20120161837Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).Type: ApplicationFiled: January 23, 2012Publication date: June 28, 2012Inventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Patent number: 8169243Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.Type: GrantFiled: April 2, 2009Date of Patent: May 1, 2012Assignee: Qualcomm IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi
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Patent number: 8140026Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.Type: GrantFiled: May 6, 2009Date of Patent: March 20, 2012Assignee: Qualcomm IncorporatedInventors: Xiaohong Quan, Lennart K. Mathe, Liang Dai, Dinesh J. Alladi
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Publication number: 20100283522Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.Type: ApplicationFiled: May 6, 2009Publication date: November 11, 2010Applicant: QUALCOMM IncorporatedInventors: Xiaohong Quan, Lennart K. Mathe, Liang Dai, Dinesh J. Alladi
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Publication number: 20100253405Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.Type: ApplicationFiled: April 2, 2009Publication date: October 7, 2010Applicant: QUALCOMM IncorporatedInventors: Xiaohong Quan, Tongyu Song, Lennart Mathe, Dinesh J. Alladi