Abstract: An apparatus and method are provide for precluding stalls in a microprocessor pipeline due to microcode ROM access delay. The apparatus includes a micro instruction queue and early access logic. The micro instruction queue provides a plurality of queue entries to register logic. Each of tile plurality of queue entries includes first micro instructions and a microcode entry point. All of the first micro instructions correspond to an instruction. The microcode entry point is coupled to the first micro instructions. The microcode entry point is configured to point to second micro instructions stored within a microcode ROM. The early access logic is coupled to the micro instruction queue.

Abstract: A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 22n?2 LSB (least significant bit) voltage levels are generated as outputs from 2n cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n?2) bits and (2n?1) bit resolution with lower SNDR are achieved by using 2n resistors and two current sources. In one described embodiment, 2n unit impedances in the cyclic string result in 2(n?1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.

Abstract: A current driven DAC architecture uses a single resistance string arranged to have a cyclic configuration and a plurality of nodes, one of the nodes being connected to a known potential, e.g., ground potential, and at least two current sources connected to selected ones of said nodes through operable switches, and an output connected to a selected one of said nodes. In one modification, 22n?2 LSB (least significant bit) voltage levels are generated as outputs from 2n cyclic string resistors and two current sources. In another modification, spurious-free resolution of (2n?2) bits and (2n?1) bit resolution with lower SNDR are achieved by using 2n resistors and two current sources. In one described embodiment, 2n unit impedances in the cyclic string result in 2(n?1) bit resolution. Thus, the single cyclic string of resistances achieves the function of both MSB sub-string and LSB sub-string.