Abstract: A system may receive an existing base set of knowledge, train a neural network on the base set of knowledge, deploy the neural network on a new data set, generate, using the deployment, instances of new knowledge, and validate the instances of new knowledge.

Abstract: An access control system controls access to a shared resource for various functional circuits. The access control system can include a comparison circuit, a processing circuit, and a selection circuit. The comparison circuit receives identification data associated with a functional circuit based on a transaction initiated by the functional circuit, and compares the identification data and reference data to generate a select signal. The processing circuit receives error data and response data outputted by the shared resource based on an execution of the transaction, and generates another response data. The selection circuit selects and outputs, based on the select signal, one of the response data outputted by the shared resource and the response data generated by the processing circuit as a transaction response that is to be provided to the functional circuit.

Abstract: An access control system controls access to a shared resource for various functional circuits. The access control system can include a comparison circuit, a processing circuit, and a selection circuit. The comparison circuit receives identification data associated with a functional circuit based on a transaction initiated by the functional circuit, and compares the identification data and reference data to generate a select signal. The processing circuit receives error data and response data outputted by the shared resource based on an execution of the transaction, and generates another response data. The selection circuit selects and outputs, based on the select signal, one of the response data outputted by the shared resource and the response data generated by the processing circuit as a transaction response that is to be provided to the functional circuit.

Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: A system-on-chip (SoC) includes a processor, a built-in self-testing (BIST) circuitry, and an adaptive masking circuitry. The processor generates a sweep enable (SWEN) signal to initiate a self-testing operation of the SoC. The BIST circuitry receives the SWEN signal and generates a set of sweep events, such that a transition of the processor from a low power (LP) mode to an active mode is initiated based on the generation of each sweep event. The BIST circuitry further receives a status signal, and identifies a subset of sweep events at which the transition of the processor from the LP mode to the active mode failed, for generating sweep failure data. The adaptive masking circuitry receives the sweep failure data and generates a mask signal, to prevent a transition of the first processor from the LP mode to the active mode, during a non-testing operation of the SoC.

Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.