Abstract: An apparatus includes a plurality of cores and a fuse array. The plurality of cores is disposed on a die. The fuse array is disposed on the die and is coupled to each of the plurality of cores, where the fuse array includes a plurality of semiconductor fuses that are programmed with compressed configuration data for the each of the plurality of cores, and where the each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: An apparatus includes a semiconductor fuse array, disposed on a die, into which is programmed configuration data. The semiconductor fuse array has a first plurality of semiconductor fuses and a second plurality of semiconductor fuses. The first plurality of semiconductor fuses is configured to store the configuration data in an encoded and compressed format. The second plurality of semiconductor fuses is configured to store first fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored.

Abstract: An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data.

Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: An apparatus for precluding the use of extended JTAG operations, including a JTAG control chain, a feature fuse, a level sensor, an access controller, and a blow controller. The JTAG control chain enables/disables the extended JTAG operations. The feature fuse indicates whether the extended JTAG features are to be disabled. The level sensor monitors an external voltage signal, and indicates that the external voltage signal is at a legal level. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown. The blow controller receives a voltage, and blows a selected fuse within a fuse array responsive to a valve of the voltage.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: A microprocessor includes a first plurality of fuses selectively blown with control values, a second plurality of fuses selectively blown collectively with an error correction value computed from the control values, control hardware that receives the control values and provides them to circuits of the microprocessor for controlling operation thereof. A state machine, serially coupled to the control hardware and to the fuses, serially scans the control values from the first fuses to the control hardware and serially scans the control values and the error correction value to a first register. The microprocessor reads the control values and error correction value from the first register, detects and corrects an error in the control values using the error correction value, writes the corrected control values to a second register, and causes the state machine to serially scan the corrected control values from the second register to the control hardware.

Abstract: An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The access controller is coupled to the feature fuse and the JTAG control chain. The access controller determines if the feature fuse is blown, and directs the JTAG control chain to disable the extended JTAG operations.

Abstract: An apparatus in an integrated circuit for precluding the use of extended JTAG operations. The apparatus has a JTAG control chain, a feature fuse, a level sensor, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The level sensor is configured to monitor an external voltage signal, and configured to indicate that the external voltage signal is at an illegal level. The access controller is coupled to the feature fuse, the level sensor, and the JTAG control chain, and is configured to determine if the feature fuse is blown, and is configured to direct the JTAG control chain to disable the extended JTAG operations if the external voltage signal is at an illegal level regardless of whether the feature fuse is blown.

Abstract: An apparatus in an integrated circuit for re-enabling the use of precluded extended JTAG operations. The apparatus includes a JTAG control chain, a feature fuse, a machine specific register, and an access controller. The JTAG control chain is configured to enable/disable the extended JTAG operations. The feature fuse is configured to indicate whether the extended JTAG features are to be disabled. The machine specific register is configured to store a value therein. The access controller is coupled to the feature fuse, the machine specific register, and the JTAG control chain, and is configured to determine that the feature fuse is blown, and is configured to direct the JTAG control chain to enable the precluded extended JTAG operations if the value matches an override value within the access controller during a period that the value is stored within the machine specific register.

Abstract: A microprocessor includes a first plurality of fuses selectively blown with control values, a second plurality of fuses selectively blown collectively with an error correction value computed from the control values, control hardware that receives the control values and provides them to circuits of the microprocessor for controlling operation thereof. A state machine, serially coupled to the control hardware and to the fuses, serially scans the control values from the first fuses to the control hardware and serially scans the control values and the error correction value to a first register. The microprocessor reads the control values and error correction value from the first register, detects and corrects an error in the control values using the error correction value, writes the corrected control values to a second register, and causes the state machine to serially scan the corrected control values from the second register to the control hardware.

Abstract: A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.

Abstract: A microprocessor includes re-writeable non-volatile state (RNS) addressable by an instruction executed by the microprocessor that instructs the microprocessor to write a new value to the RNS. A plurality of fuses are each readable to determine whether the fuse is blown or unblown, in response to the microprocessor decoding the instruction. A Boolean logic unit performs Boolean operations on the values read from the plurality of fuses to determine a current RNS value. A fuse blowing device blows at least one unblown fuse to change the current RNS value to the new value when the new value is different than the current value. The microprocessor can read the plurality of fuses, perform the Boolean operations, and blow at least one unblown fuse to change the current value of the RNS to a new value multiple times in response to a program running on the microprocessor executing the instruction multiple times.

Abstract: An apparatus and method are provide for precluding stalls in a microprocessor pipeline due to microcode ROM access delay. The apparatus includes a micro instruction queue and early access logic. The micro instruction queue provides a plurality of queue entries to register logic. Each of the plurality of queue entries includes first micro instructions and a microcode entry point. All of the first micro instructions correspond to an instruction. The microcode entry point is coupled to the first micro instructions. The microcode entry point is configured to point to second micro instructions stored within a microcode ROM. The early access logic is coupled to the micro instruction queue.

Abstract: An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro instructions in the same clock cycle as the pairing if a resource conflict or operand dependency is detected. The apparatus includes multiplexing logic that feeds back a second of a pair of micro instructions stored in an instruction register back into the instruction register for sequential execution after the first micro instruction if a translator detects late in the clock cycle that a resource conflict or operand dependency exists. An instruction pair indicator is provided along with the pair of micro instructions down to the execution stages to inform the execution stages whether the second micro instruction is valid for parallel execution with the first micro instruction. The method may also be used in conjunction with a micro instruction queue.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.