Patents by Inventor Dinesh K. Penigalapati
Dinesh K. Penigalapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8524606Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.Type: GrantFiled: January 25, 2011Date of Patent: September 3, 2013Assignees: International Business Machines Corporation, JSR CorporationInventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Patent number: 8513127Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.Type: GrantFiled: January 25, 2011Date of Patent: August 20, 2013Assignees: International Business Machines Corporation, JSR CorporationInventors: Josephine B. Chang, Leslie Charns, Jason E. Cummings, Michael A. Guillorn, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Patent number: 8507383Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.Type: GrantFiled: January 25, 2011Date of Patent: August 13, 2013Assignees: International Business Machines Corporation, JRS CorporationInventors: Takashi Ando, Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Patent number: 8497210Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.Type: GrantFiled: January 24, 2011Date of Patent: July 30, 2013Assignees: International Business Machines Corporation, JRS CorporationInventors: Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20120083122Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.Type: ApplicationFiled: January 24, 2011Publication date: April 5, 2012Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20120083123Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.Type: ApplicationFiled: January 25, 2011Publication date: April 5, 2012Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Leslie Charns, Jason E. Cummings, Michael A. Guillorn, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20120083121Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.Type: ApplicationFiled: January 25, 2011Publication date: April 5, 2012Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
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Publication number: 20120083125Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.Type: ApplicationFiled: January 25, 2011Publication date: April 5, 2012Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lafaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka