Abstract: A method includes receiving, at a bitline-mux driver circuit, a subarray activation (SUBA) signal and a delay signal. The bitline-mux driver circuit includes a header circuit operable to output a driver voltage to a plurality of driver circuits. The driver voltage is boosted through a voltage divider with diode header circuit based on the SUBA signal to set the driver voltage to a value above a standard supply voltage (VDD) and between a voltage bitline high (VBLH) level and a high voltage (VPP) level. The VPP level exceeds a maximum allowed voltage (VMAX) level of the driver circuits. A master wordline output of the driver circuits is driven to select a bitline mux of a computer memory module based on an address input signal, the delay signal, and the driver voltage.

Abstract: A method includes receiving, at a bitline-mux driver circuit, a subarray activation (SUBA) signal and a delay signal. The bitline-mux driver circuit includes a header circuit operable to output a driver voltage to a plurality of driver circuits. The driver voltage is boosted through a voltage divider with diode header circuit based on the SUBA signal to set the driver voltage to a value above a standard supply voltage (VDD) and between a voltage bitline high (VBLH) level and a high voltage (VPP) level. The VPP level exceeds a maximum allowed voltage (VMAX) level of the driver circuits. A master wordline output of the driver circuits is driven to select a bitline mux of a computer memory module based on an address input signal, the delay signal, and the driver voltage.

Abstract: Techniques for voltage bitline high (VBLH) regulation for a computer memory are described herein. An aspect includes generating, by a resistor ladder and a diode compensation footer, a VBLH reference signal based on a high voltage (VPP) in a computer memory module. Another aspect includes regulating a VBLH signal based on the VBLH reference signal. Another aspect includes regulating a wordline driver voltage of the computer memory module based on the VBLH signal.

Abstract: Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.