Abstract: A circuit for realizing a precision and linear floating resistor, using MOSFET devices, is disclosed. A linear floating voltage-controlled resistor (LFVCR) is realized using a MOSFET with a gate drive means and a substrate drive means to provide a feedback of the common-mode voltage across the source-drain terminals to the gate and substrate terminals. Two such LFVCR circuits using matched MOSFET devices having independent substrates, along with an op-amp based negative feedback loop, are used to realize a continuously variable precision and linear floating resistor, whose value can be controlled by a combination of variable voltage, current, and resistor. Further embodiments are disclosed for realizing a resistor mirror circuit with multiple floating resistors, improving the linearity by using LFVCR circuits with complementary MOSFET devices, realizing a resistor with scaled-up resistance and extended voltage range, and realizing a resistor with scaled-down resistance and extended current range.

Abstract: A circuit for realizing a precision and linear floating resistor, using MOSFET devices, is disclosed. A linear floating voltage-controlled resistor (LFVCR) is realized using a MOSFET with a gate drive means and a substrate drive means to provide a feedback of the common-mode voltage across the source-drain terminals to the gate and substrate terminals. Two such LFVCR circuits using matched MOSFET devices having independent substrates, along with an op-amp based negative feedback loop, are used to realize a continuously variable precision and linear floating resistor, whose value can be controlled by a combination of variable voltage, current, and resistor. Further embodiments are disclosed for realizing a resistor mirror circuit with multiple floating resistors, improving the linearity by using LFVCR circuits with complementary MOSFET devices, realizing a resistor with scaled-up resistance and extended voltage range, and realizing a resistor with scaled-down resistance and extended current range.

Abstract: In some embodiments, a method receives a plurality of portions of recognized speech from a plurality of devices. Each portion includes an associated confidence score and time stamp. For one or more time stamps associated with the plurality of portions, the method identifies two or more confidence scores for two or more of the plurality of portions of recognized speech. For the one or more time stamps, one of the two or more of the plurality of portions of recognized speech is selected based on the two or more confidence scores for the two or more of the plurality of portions. The method generates a transcript using the one of the two or more of the plurality of portions of recognized speech selected for the respective one or more time stamps.

Abstract: The present invention involves an improved process for the preparation of Indocyanine green of Formula (I) having high purity of about 99%, wherein the process comprises steps of reacting 1,1,2-trimethyl-1H-benzo[e]indole with 1,4-butane sulfone in boiling solvent to give 4-(1,1,2-trimethyl-1H-benzo[e]indolium-3-yl)butane-1-sulfonate. Followed by reacting 4-(1,1,2-trimethyl-1H-benzo[e]indolium-3-yl)butane-1-sulfonate of Formula (IV) and N-phenyl-N-((1E,3E,5E)-5-(phenylimino)penta-1,3-dienyl)acetamide of formula (V) in presence of sodium acetate and alcohol; and extracting the title compound formula (I) with an ester solvent.

Abstract: The present invention involves an improved process for the preparation of Indocyanine green of Formula (I) having high purity of about 99%, wherein the process comprises steps of reacting 1,1,2-trimethyl-1H-benzo[e]indole with 1,4-butane sulfone in boiling solvent to give 4-(1,1,2-trimethyl-1H-benzo[e]indolium-3-yl)butane-1-sulfonate. Followed by reacting 4-(1,1,2-trimethyl-1H-benzo[e]indolium-3-yl)butane-1-sulfonate of Formula (IV) and N-phenyl-N-((1E,3E,5E)-5-(phenylimino)penta-1,3-dienyl)acetamide of formula (V) in presence of sodium acetate and alcohol; and extracting the title compound formula (I) with an ester solvent.

Abstract: A nonvolatile floating gate analog memory cell (1) comprising a transistor having a source (2) and drain (3) formed inside a substrate or on an insulator body (not shown) and separated by a channel (4). The memory cell comprises at least one floating gate (5) formed on one side of the source and drain. (6) is a control gate formed on one side of the floating gate and connected to a first voltage (7). (8) is a back gate formed on the other side of the source and drain and connected to a second voltage (9). The channel is separated from the floating gate and the back gate by an insulation layer (10). The control gate is separated from the floating gate by an insulation layer (11) and the source and drain are isolated from the back gate, control gate and floating gate(s) by a spacer (12). The second voltage changes the intrinsic threshold voltage linearly during programming so that the programmed threshold voltage corresponds to the second voltage.

Abstract: A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/?s vs. 273 V/?s), with minimal increases in power dissipation (78 ?W vs. 46 ?W).

Abstract: A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/?s vs. 273 V/?s), with minimal increases in power dissipation (78 ?W vs. 46 ?W).

Abstract: A nonvolatile floating gate analog memory cell (1) comprising a transistor having a source (2) and drain (3) formed inside a substrate or on an insulator body (not shown) and separated by a channel (4). The memory cell comprises at least one floating gate (5) formed on one side of the source and drain. (6) is a control gate formed on one side of the floating gate and connected to a first voltage (7). (8) is a back gate formed on the other side of the source and drain and connected to a second voltage (9). The channel is separated from the floating gate and the back gate by an insulation layer (10). The control gate is separated from the floating gate by an insulation layer (11) and the source and drain are isolated from the back gate, control gate and floating gate(s) by a spacer (12). The second voltage changes the intrinsic threshold voltage linearly during programming so that the programmed threshold voltage corresponds to the second voltage.