Abstract: In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks.

Abstract: In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks.