Abstract: A touch-sensing module is disclosed. The touch-sensing module includes: a substrate having a first region, a second region and a flexible region configured between the first region and the second region so as to enable the touch-sensing module to have a folded state and an unfolded state; and a sensing layer configured under the substrate and having a first sensing pattern layer and a second sensing pattern layer, wherein the first sensing pattern layer corresponds to the first region and the second sensing pattern layer corresponds to the second region.

Abstract: A touch-sensing module is disclosed. The touch-sensing module includes: a substrate having a first region, a second region and a flexible region configured between the first region and the second region so as to enable the touch-sensing module to have a folded state and an unfolded state; and a sensing layer configured under the substrate and having a first sensing pattern layer and a second sensing pattern layer, wherein the first sensing pattern layer corresponds to the first region and the second sensing pattern layer corresponds to the second region.

Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.

Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.

Abstract: Interconnect structures with polygonal cell structures. An exemplary interconnect structure comprises a substrate and a first dielectric layer, overlying the substrate and exposing a conductive feature formed therethrough and connected with the substrate, wherein the first dielectric layer includes a plurality of polygon cell structures with hollow interior.

Abstract: A direct printing lithography system for jet-printing a photoresist on a layer in the form of a desired circuit pattern is disclosed. The system includes a computer system for containing a programmed circuit pattern and generating printing signals and a jet printing head for receiving the printing signals from the computer system and printing the photoresist on the layer in the form of the programmed circuit pattern. A direct printing lithography method is also disclosed.

Abstract: Interconnect structures with polygonal cell structures. An exemplary interconnect structure comprises a substrate and a first dielectric layer, overlying the substrate and exposing a conductive feature formed therethrough and connected with the substrate, wherein the first dielectric layer includes a plurality of polygon cell structures with hollow interior.

Abstract: Methods and compositions are described for liquid or gel forms of a lipid excipient to be used in pharmaceutical or cosmetic preparations. The lipid excipient comprises a phospholipid such as a lysophospholipid, for example, mono-oleoyl-phosphatidylethanolamine ("MOPE"). Relatively low concentrations of the lipid can be employed in forming the gel, e.g., about 1-2%. The invention discloses the use of a lipid delivery system at a relatively low lipid concentration as a non-toxic, non-irritating carrier or excipient alone or in combination with other agents, for both drugs and cosmetics. For example, the lipid excipient in sprayable or droppable form has special utility in the non-irritating delivery of peptides (e.g., calcitonin and insulin) to the nasal mucosa, due to the ability of the excipient to enhance absorption across nasal membranes. As a cosmetic, it can be used alone or in combination with biologically active agents.