Abstract: Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.

Abstract: Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.

Abstract: A method and devices are provided for producing a non-volatile SRAM, of the type composed of two back-to-back, cross-coupled, CMOS inverters, each with a PMOS and an NMOS and respective outputs Q and Q.about. connected therebetween, even when the cell is completely symmetrical, by creating a stable condition wherein Q.noteq.Q.about. through rendering the threshold voltages of the NMOS devices different. The threshold voltages of the NMOSs are made different by using hot electron injection. The hot electron effect is produced by meeting the conditions, that 1) one of the NMOSs must be in saturation condition, i.e., V.sub.DS .gtoreq.V.sub.GS -V.sub.th, where V.sub.DS is the drain to source voltage, V.sub.GS is the gate to source voltage, and V.sub.th the threshold voltage, of the NMOS, and 2) V.sub.DS must be large enough, typically about 7 V, depending on the fabrication process.