Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.

Abstract: An optical recording system includes a laser light source that provides an incident recording light signal for recording information on an optical recording medium, an optical detector for detecting a reflected write pulse from the optical recording medium, and a light source controller for controlling recording laser beam power of the laser light source according to a mark formation effectiveness signal generated by a signal generating device. The signal generating device includes an analog peak value detector for detecting a peak value of the reflected write pulse from the optical detector, at least one sample-hold circuit for sampling the reflected write pulse to obtain at least one amplitude value, and a processor for generating the mark formation effectiveness signal according to the peak value and the amplitude value.

Abstract: In a method and apparatus for enabling fast clock phase locking in a phase-locked loop, a sampling clock generator generates sampling clock signals in response to an oscillator output of the phase-locked loop. A detector unit samples an input digital signal to the phase-locked loop at clock edges of the sampling clock signals to obtain multiple sampling points of the input digital signal, and compares logic levels of each temporally adjacent pair of the sampling points to detect presence of a logic level transition in the input digital signal. A selector unit is controlled by the detector unit to select one of the sampling clock signals, which has one of the clock edges thereof defining an interval that was detected to have occurrence of the logic level transition in the input digital signal, and which is subsequently provided to the phase-locked loop as an input phase-locking clock signal.

Abstract: An optical recording system includes a laser light source that provides an incident recording light signal for recording information on an optical recording medium, an optical detector for detecting a reflected write pulse from the optical recording medium, and a light source controller for controlling recording laser beam power of the laser light source according to a mark formation effectiveness signal generated by a signal generating device. The signal generating device includes an analog peak value detector for detecting a peak value of the reflected write pulse from the optical detector, at least one sample-hold circuit for sampling the reflected write pulse to obtain at least one amplitude value, and a processor for generating the mark formation effectiveness signal according to the peak value and the amplitude value.

Abstract: A differential-type voltage-controlled oscillator (VCO) with low-frequency stability compensation is disclosed. The differential-type VCO comprises a voltage-to-current converter for converting an input voltage signal into a biasing current signal to control the frequency of the VCO output. The VCO further comprises a number of stages of differential amplifiers connected in cascade. Each of the stages of differential amplifiers includes a pair of differential input PMOS transistors, with each of the PMOS transistors connected to a pair of NMOS load transistors. Each of the pair of NMOS load transistors are connected in parallel. The VCO further comprises a number of stages of bias circuits connected in cascade. Each of the bias circuits is connected to a corresponding stage of the differential amplifiers for receiving the bias current generated by the voltage-to-current converter.

Abstract: A bias circuit for virtual ground non-volatile memory array with bank selector, utilizes static pull-up transistors connected respectively to all bit lines of the memory array. The gates of the static pull-up transistors are connected to a predetermined reference voltage for supplying a global bias voltage to the bit lines. Another predetermined reference voltage, acting as a local bias voltage, is supplied to a deselected virtual ground bit line which is adjacent to the selected data sense bit line. By these two bias techniques, the leakage current of the adjacent deselected "ON" memory cells is minimized; as a result, the stability of the current detector is largely enhanced; the probability of erroneous data reading is reduced; the operating voltage margin of the memory devices is enlarged; and the data accessing is expedited.

Abstract: A two-phase sense amplifier includes a data sensing circuitry including a presetting current detecting circuit for allowing the sense amplifier to be in a presetting phase when an X-decoder decodes an address of a selected word line of a selected memory cell and a Y-decoder decodes an address of a selected bit line of the selected memory cell and then for setting a voltage level of the selected bit line to be around a switching point and an evaluating current detecting circuit for allowing the sense amplifier to be in an evaluating phase after the voltage level of the selected bit line is around the switching point in order to sense a current in the selected cell for converting the current into a voltage output, a dummy cell circuitry electrically connected to the data sensing circuitry for providing a reference voltage to the data sensing circuitry, and a differential amplifier electrically connected to the data sensing circuitry and the dummy cell circuitry for accepting and comparing the voltage output and

Abstract: A current sense circuit with fast response for sensing a current input from a current source such as a memory cell, comprising a first amplifying means and a second amplifying means coupled to a first transistor and a second transistor, respectively. The first transistor is smaller in size than the second transistor and the reference voltage of the first amplifying means is slightly larger than the reference voltage of the second amplifying means. A load is coupled to the drain of the first transistor.