Abstract: A method of operating a set of ferroelectric memory cells is provided. The method may include, in a first cycle, writing a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells. The method may include, in the first cycle, writing a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells. The set of sign bits may indicate a polarity of the set of ferroelectric memory cells. The method may include, in a second cycle subsequent to the first cycle, reading the set of sign bits from the at least one second ferroelectric memory cell. The method may include, in the second cycle, performing an error-correction operation on the set of sign bits to determine the first value of the set of sign bits written in the first cycle.

Abstract: According to one aspect of the present disclosure, a method of operating a set of ferroelectric memory cells is provided. The method may include, in a first cycle, writing a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells. The method may include, in the first cycle, writing a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells. The set of sign bits may indicate a polarity of the set of ferroelectric memory cells. The method may include, in a second cycle subsequent to the first cycle, reading the set of sign bits from the at least one second ferroelectric memory cell. The method may include, in the second cycle, performing an error-correction operation on the set of sign bits to determine the first value of the set of sign bits written in the first cycle.

Abstract: There is provided a method of correcting over-erased memory cells in a flash EPROM memory device so as to achieve zero column leakage after erase. A ground potential is applied to all of the word lines in the memory device. First positive pulse voltages are applied to each bit line on a bit line by bit line basis until the column leakage current in each bit line is reduced to a relatively small value. Thereafter, a positive bias voltage is applied to each word line in a first timed sequence on a word line by word line basis. Second positive pulse voltages are simultaneously applied to each bit line in a second timed sequence on a bit line by bit line basis when the positive bias voltage is being applied to a first word line until the column leakage current in the corresponding bit line is reduced to zero and is then repeated for each subsequent remaining word line.