Patents by Inventor Ding Yi

Ding Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6803305
    Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: October 12, 2004
    Assignee: Chartered Semiconductor Manufacturing Limited
    Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Ding Yi
  • Publication number: 20030194856
    Abstract: A method for forming a via in a damascene process. In one embodiment, the present method comprises depositing a material into a via formed using a damascene process. More particularly, in one embodiment, the material which is comprised of a substantially conformal material which has an etch selectivity with respect to the substrate into which the via is formed. Furthermore, in this embodiment, the material is deposited along the sidewalls and the base of the via. Next, the present embodiment etches material such that the via is formed having a profile conducive to the adherence of overlying material thereto. In this embodiment, the etching of the material is performed without substantially etching the substrate into which the via is formed. In so doing, the present embodiment creates a via in a damascene process which allows for the formation of a metallized interconnect which is substantially free of voids.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 16, 2003
    Inventors: Daniel Yen, Wei Hua Cheng, Yakub Aliyu, Ding Yi
  • Patent number: 6441676
    Abstract: A method for programming an antifuse circuit that includes a capacitor and a detector. The capacitor is formed using standard MOS processes in a well. The gate serves as one electrode and the well serves as another electrode of the capacitor. The antifuse is programmed by eternally provided radiation that can rupture the gate oxide so that the gate and the well can contact each other. The gate and well form a PN junction, transforming the capacitor into a diode. The diode provides the conductive path of the programmed antifuse.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: August 27, 2002
    Assignee: Intel Corporation
    Inventors: Sean M. Koehl, Dean Samara-Rubio, Ding Yi