Patents by Inventor Ding-Yuan S. Day

Ding-Yuan S. Day has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4978639
    Abstract: Metallized via-holes and a wraparound metal plating are simultaneously formed on semiconductor chips by patterning a photoresist mask on the front surface of the wafer to open windows over metal pads as well as the grid areas where wraparound plating is desired; etching off the exposed metal if necessary and forming via-holes and grooves in the wafer by reactive ion etching to a depth which is less than the total thickness of the wafer; depositing a thin conductive film along the walls of the grooves and via-holes by electroless methods; plating the walls of the grooves and the via-holes with conductive metal by electrolytic methods; removing the back surface of the wafer ("backlapping") along with the floors of both the grooves and the via-holes, to expose the metal on the wall of the via-holes and separate the individual chips; and, depositing conductive metal on the back surface of the individual chips to complete the grounding path.
    Type: Grant
    Filed: January 10, 1989
    Date of Patent: December 18, 1990
    Assignee: Avantek, Inc.
    Inventors: Chang-Hwang Hua, Simon S. Chan, Ding-Yuan S. Day, Adrian C. Lee
  • Patent number: 4842699
    Abstract: A method for simultaneous selective plating of viaholes and heat sinks associated with a semiconductor wafer using a metal mask and comprising the steps of:(a) coating a first side of the wafer with an insulating layer to prevent electroplating on this first side;(b) patterning on a second side of the wafer, opposite to the first side, a metal mask for defining the areas where plating should not occur;(c) forming via-holes through said wafer;(d) depositing a thin conductive film to coat the bottom and walls of the via-holes as well as areas of the second side of the wafer not covered by the metal mask; and(e) electrolytically plating the resulting wafer while ultrasonically agitating the electrolyte if necessary to ensure sufficient electrolyte transport into the via-holes for uniform plating.
    Type: Grant
    Filed: May 10, 1988
    Date of Patent: June 27, 1989
    Assignee: Avantek, Inc.
    Inventors: Chang-Hwang Hua, Ding-Yuan S. Day, Simon S. Chan
  • Patent number: 4808273
    Abstract: A method is disclosed for forming completely metallized via holes in semiconductor wafers. Metal pads are formed on one face of a semiconductor wafer together with a conductive interconnecting network. An insulating layer is then deposited to cover this face of the wafer. Holes are etched in the opposite face of the wafer up to and exposing a portion of the metal pads. The via holes are then completely filled with metal by means of electroplating, using the metal pads as a cathode.
    Type: Grant
    Filed: May 10, 1988
    Date of Patent: February 28, 1989
    Assignee: Avantek, Inc.
    Inventors: Chang-Hwang Hua, Ding-Yuan S. Day, Simon S. Chan