Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, having a first surface; a plurality of memory cells, located on the first surface of the substrate and arranged according to a first preset pattern; and a plurality of memory contact structures, corresponding to the memory cells in a one-to-one manner, where bottom portions of the memory contact structures are in contact with top portions of the memory cells, and top portions of the memory contact structures are arranged according to a second preset pattern. The bottom portion of the memory contact structure is arranged opposite to the top portion of the memory contact structure.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the substrate, wherein a channel material of the vertical transistor includes an oxide semiconductor. A plurality of staggered contact pads connected to upper ends of the vertical transistors are formed on the vertical transistors, wherein a single contact pad is connected to the upper ends of an even number of vertical transistors. A magnetic tunnel junction is formed on the contact pad.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a plurality of memory cells alternately arranged on a substrate, the memory cell including an odd number of vertical transistors, a connection pad connected to one end of each of the odd number of vertical transistors, and a magnetic tunnel junction located on the connection pad; wherein a material of a channel of the vertical transistor includes a monocrystalline semiconductor.

Abstract: A semiconductor structure, a manufacturing method therefor and a memory are provided. The semiconductor structure may at least include: a plurality of aligned transistors, in which the transistors share a same source plate, channels of the transistors are located above the source plate, the channel length direction of the transistors is perpendicular to a surface of the source plate, and a material of the channels includes a single crystal semiconductor; a plurality of drain contacts, electrically connected with drains of the transistors, in which even number of the transistors share one same drain contact; and a plurality of magnetic tunnel junctions, located on the drain contacts and electrically connected with the drain contacts in one-to-one correspondence.

Abstract: A method for manufacturing a semiconductor structure, a semiconductor structure and a semiconductor memory are provided. The method includes: providing a substrate; forming an MTJ structure and a first mask structure sequentially on the substrate; patterning the first mask structure to form a first pattern extending in a first direction; forming a second mask structure on the first pattern; patterning the second mask structure to form a second pattern extending in a second direction, in which the first direction intersects the second direction, and is not perpendicular to the second direction; patterning the first pattern by utilizing the second pattern to form a cellular pattern; and transferring the cellular pattern to the MTJ structure to form a cellular MTJ array.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

Abstract: The present application relates to a memory device and a preparing method thereof. The memory device includes: a substrate, and a plurality of memory cells disposed in an array on the substrate. Memory cells in adjacent rows are staggered in a row direction, and a distance between two adjacent memory cells in any row is a first distance. Memory cells in adjacent columns are staggered in a column direction, and a staggered distance is less than the first distance.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: The disclosure relates generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more generally to structures and methods of fabricating multiple conductive elements in ReRAM devices. A resistive memory device is presented, the device comprising a first electrode having a first work function, and a second electrode having a second work function, the first work function being different from the second work function. A dielectric layer is disposed between the first and second electrodes. The device further comprises a set of nanocrystal structures distributed in the dielectric layer. A conductive layer is also disposed in the dielectric layer.

Abstract: Spin transfer torque magnetic random access memory structures, integrated circuits, and methods for fabricating integrated circuits are provided. An exemplary spin transfer torque magnetic random access memory structure has a perpendicular magnetic orientation, and includes a bottom electrode and a base layer over the bottom electrode. The spin transfer torque magnetic random access memory structure further includes a fixed layer over the base layer. The fixed layer includes anti-parallel layers including cobalt tungsten/platinum (CoW/Pt) bilayers, cobalt molybdenum/platinum (CoMo/Pt) bilayers, or bilayers including a combination of at least two materials selected from cobalt (Co), tungsten (W), molybdenum (Mo), platinum (Pt), palladium (Pd) or iridium (Ir). Also, the spin transfer torque magnetic random access memory structure includes a magnetic tunnel junction (MTJ) element with a perpendicular orientation over the fixed layer and a top electrode over the MTJ element.