Abstract: Embodiments include herein are directed towards a method for electronic circuit design and more specifically towards determining return path quality in an electrical circuit. Embodiments may include providing, using a processor, an electronic circuit design and identifying at least one net associated with the electronic circuit design. Embodiments may further include extracting an ideal loop inductance for the at least one net and extracting a real loop inductance for the at least one net. Embodiments may also include calculating a return path quality factor based upon, at least in part, the ideal loop inductance and the real loop inductance.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified through a graphical design interface. Certain of the structures of the physical system may be partitioned into a subsystem such that the data describing the subsystem includes physical topology data defining relative locations of the structures in the physical system. The physical topology data is back-annotated into a logical topology, such as in accordance with a predefined logical topology template. The logical data abstraction of the circuit design is kept synchronized with the physical data and presented in a logical topology that is kept legible through the prudent selection of logical topologies representing the physical subsystem design.

Abstract: A design system provides data structures to store parameters of physical structures that can be viewed and modified in a front-end process through a logical design interface. In this way, system behavior defined by component structure can be evaluated and modified through a schematic representation of the data, regardless of a state of data representing the physical layout of interconnected physical structures. In electric circuit applications, for example, high frequency circuits can be incrementally designed and evaluated through structural parameters defined in a schematic diagram data abstraction without modifying and evaluating a layout data abstraction of the circuit directly.