Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

Abstract: A lateral power semiconductor device layout and a device structure belong to the technical field of power semiconductor devices. A method for designing a lateral power semiconductor device layout with high integrity and high cell density has the following advantages of reducing a specific on-resistance of the device, increasing a width of a channel per unit area, improving the current capability of the device, optimizing the static characteristic of the device, reducing the area of a drain region and the parasitic capacitance of the device, reducing the delay time of a cell switch caused by an excessively long gate electrode of a traditional finger cell, optimizing the dynamic characteristic of the device, optimizing the cell edge of the device and the curvature effect of a terminal, and reducing the pre-breakdown risk of the device.

Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

Abstract: A power semiconductor device for improving a hot carrier injection is provided. A drain field plate is introduced at one side of a drain in a dielectric trench and connected to a drain electrode, having identical electric potential, thereby improving hole injection effects at a drain side of the dielectric trench. A shield gate field plate is introduced at one side of a source electrode in the dielectric trench and is connected to the source electrode or ground, thereby forming a shield gate. While decreasing gate drain parasitic capacitance Cgd, electron injection effects at a source electrode side of the dielectric trench are improved. With a trench etching method, the improvement of hot carrier injection can also be achieved by making carriers avoid a side wall of the dielectric trench on a path.