Abstract: An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.

Abstract: A microfluidic chip for culturing and real-time monitoring of multicellular tissues and use method thereof. The chip comprises a glass substrate layer, and a PDMS microchannel layer located on the glass substrate layer, wherein the glass substrate layer comprises a glass substrate, and a plurality of microelectrodes thereon; the PDMS microchannel comprises a plurality of independent microfluidic channels; the microelectrodes on the glass substrate are in one-to-one correspondence with the microfluidic channels in the PDMS microchannel layer; and the microelectrodes are electrically connected to an external circuit. The use method comprises: cell capture, cell or tissue culture, electrical impedance spectroscopy detection, and tissue release.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Abstract: An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.

Abstract: A microfluidic chip for culturing and real-time monitoring of multicellular tissues and use method thereof. The chip comprises a glass substrate layer, and a PDMS microchannel layer located on the glass substrate layer, wherein the glass substrate layer comprises a glass substrate, and a plurality of microelectrodes thereon; the PDMS microchannel comprises a plurality of independent microfluidic channels; the microelectrodes on the glass substrate are in one-to-one correspondence with the microfluidic channels in the PDMS microchannel layer; and the microelectrodes are electrically connected to an external circuit. The use method comprises: cell capture, cell or tissue culture, electrical impedance spectroscopy detection, and tissue release.