Patents by Inventor Dingying David Xu
Dingying David Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250112164Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Onur OZKAN, Ryan CARRAZZONE, Rui ZHANG, Haobo CHEN, Ziyin LIN, Yiqun BAI, Kyle ARRINGTON, Jose WAIMIN, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Venkata Rajesh SARANAM, Shripad GOKHALE, Kartik SRINIVASAN, Edvin CETEGEN, Mine KAYA, Nicholas S. HAEHN, Deniz TURAN
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Publication number: 20250106983Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Bohan SHAN, Kyle ARRINGTON, Dingying David XU, Ziyin LIN, Timothy GOSSELIN, Elah BOZORG-GRAYELI, Aravindha ANTONISWAMY, Wei LI, Haobo CHEN, Yiqun BAI, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Bin MU, Mohit GUPTA, Jeremy D. ECTON, Brandon C. MARIN, Xiaoying GUO, Ashay DANI
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Patent number: 12230563Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: September 29, 2022Date of Patent: February 18, 2025Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20240363520Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate with a layer on the substrate. In an embodiment, the layer comprises a plurality of wells. In an embodiment, a liquid metal is in the plurality of wells. In an embodiment, a cap is on the layer to seal the plurality of wells, where the cap comprises a polymer, and fibers within the polymer.Type: ApplicationFiled: April 25, 2023Publication date: October 31, 2024Inventors: Ziyin LIN, Boer LIU, Dingying David XU, Karumbu MEYYAPPAN
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Publication number: 20240321807Abstract: Embodiments disclosed herein include multi-die modules. In an embodiment, the multi-die module comprises a first die and a second die coupled to the first die. In an embodiment, the second die comprises a keep out zone that at least partially overlaps the first die. The multi-die module may further comprise an underfill between the first die and the second die. In an embodiment, the underfill is entirely outside the keep out zone, and an edge of the underfill facing the keep out zone is non-vertical.Type: ApplicationFiled: March 20, 2023Publication date: September 26, 2024Inventors: Jonas CROISSANT, Xavier F. BRUN, Gustavo BELTRAN, Roberto SERNA, Ye Seul NAM, Timothy GOSSELIN, Jesus S. NIETO PESCADOR, Dingying David XU, John C. DECKER, Ifeanyi OKAFOR, Yiqun BAI
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Publication number: 20240071848Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Bohan SHAN, Haobo CHEN, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Bai NIE, Gang DUAN, Kyle ARRINGTON, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying David XU, Jeremy D. ECTON, Kristof DARMAWIKARTA, Suddhasattwa NAD
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Publication number: 20230317653Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 30, 2022Publication date: October 5, 2023Inventors: Hongxia FENG, Xiaoxuan SUN, Amey Anant APTE, Dingying David XU, Sairam AGRAHARAM, Gang DUAN, Ashay DANI
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Publication number: 20230307379Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Phil GENG, Patrick NARDI, Ravindranath V. MAHAJAN, Dingying David XU, Prasanna RAGHAVAN, John HARPER, Sanjoy SAHA, Yang JIAO
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Patent number: 11676891Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: June 30, 2021Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20210327800Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
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Patent number: 11088062Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: GrantFiled: July 19, 2017Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Hongxia Feng, Dingying David Xu, Sheng C. Li, Matthew L. Tingey, Meizi Jiao, Chung Kwang Christopher Tan
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Publication number: 20190027431Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Hongxia FENG, Dingying David XU, Sheng C. LI, Matthew L. TINGEY, Meizi JIAO, Chung Kwang Christopher TAN
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Patent number: 10168357Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.Type: GrantFiled: December 21, 2015Date of Patent: January 1, 2019Assignee: Intel CorporationInventors: Wen Yin, Anna M. Prakash, Teag R. Haughan, Dingying David Xu, Joaquin Aguilar-Santillan
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Publication number: 20170176516Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: Mohit Mamodia, Kyle Yazzie, Dingying David Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
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Publication number: 20170176495Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: Wen Yin, Anna M. Prakash, Teag R. Haughan, Dingying David Xu, Joaquin Aguilar-Santillan
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Patent number: 9659889Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.Type: GrantFiled: December 20, 2013Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Mihir Oka, Xavier Brun, Dingying David Xu, Edward Prack, Kabirkumar Mirpuri, Saikumar Jayaraman
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Publication number: 20150179595Abstract: This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: Mihir Oka, Xavier Brun, Dingying David Xu, Edward Prack, Kabirkumar Mirpuri, Saikumar Jayaraman