Patents by Inventor Dingying Xu

Dingying Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153837
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.
    Type: Application
    Filed: November 8, 2022
    Publication date: May 9, 2024
    Inventors: Ziyin LIN, Vipul MEHTA, Jonas CROISSANT, Jigneshkumar PATEL, Dingying XU, Gang DUAN, Aditya Sumanth YERRAMILLI, Suriyakala RAMALINGAM, Xavier BRUN
  • Publication number: 20240112971
    Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
  • Publication number: 20240088052
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Patent number: 11923312
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Srinivas Pietambaram, Jesse Jones, Yosuke Kanaoka, Hongxia Feng, Dingying Xu, Rahul Manepalli, Sameer Paital, Kristof Darmawikarta, Yonggang Li, Meizi Jiao, Chong Zhang, Matthew Tingey, Jung Kyu Han, Haobo Chen
  • Publication number: 20240074046
    Abstract: Technologies for integrated circuit components with liquid metal interconnects are disclosed. In the illustrative embodiment, a bed of nails socket can mate with an integrated circuit component with liquid metal interconnects. The nails pierce a foam cap layer that seals the liquid metal interconnects, electrically coupling the nails to the liquid metal interconnects. A fabric layer adjacent to the foam cap layer helps secure the foam cap layer, preventing small pieces of the foam cap layer that may be dislodged during repeated insertion into a bed of nails socket from becoming separated from the foam cap layer. The fabric layer can provide additional benefits, such as removing more of the liquid metal from the nails when the integrated circuit component is removed from the bed of nails socket.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Karumbu Nathan Meyyappan, Dingying Xu
  • Publication number: 20230317619
    Abstract: A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Ravindranath V. Mahajan, Srikant Nekkanty, Srinivas V. Pietambaram, Veronica Strong, Xiao Lu, Tarek A. Ibrahim, Karumbu Nathan Meyyappan, Dingying Xu, Kristof Darmawikarta
  • Publication number: 20230290661
    Abstract: The present disclosure relates to a tray assembly. The tray assembly may include a die transport tray. The die transport tray may include an inner bottom surface for accommodating a plurality of dies. The tray assembly may further include a lid. The lid may include an inner top surface, wherein the inner top surface of the lid may face the inner bottom surface of the die transport tray when the lid is assembled over the die transport tray. The lid may further include a shock absorbing material on the inner top surface for contacting the plurality of dies, if present.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: Kyle ARRINGTON, Kirk WHEELER, Emily SCHUBERT, Dingying XU, Bassam ZIADEH
  • Publication number: 20230187850
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a socket that includes one or more liquid metal filled reservoirs. In selected examples, the electronic devices and sockets include configurations to aid in reducing ingress of moisture.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Ziyin Lin, Aaron Michael Garelick, Karumbu Meyyappan, Gregorio Murtagian, Srikant Nekkanty, Taylor Rawlings, Jeffory L. Smalley, Pooya Tadayon, Dingying Xu
  • Publication number: 20230187337
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes liquid metal pathways that form one or more conduction pathway through one or more dielectric layers. In selected examples, the dielectric layers are resilient, which allows for flexibility of interconnect components.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 15, 2023
    Inventors: Karumbu Meyyappan, Srikant Nekkanty, Gregorio Murtagian, Pooya Tadayon, Ziyin Lin, Eric J.M. Moret, Jeffory L. Smalley, Dingying Xu
  • Publication number: 20230137877
    Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 4, 2023
    Inventors: Bohan SHAN, Haobo CHEN, Omkar KARHADE, Malavarayan SANKARASUBRAMANIAN, Dingying XU, Gang DUAN, Bai NIE, Xiaoying GUO, Kristof DARMAWIKARTA, Hongxia FENG, Srinivas PIETAMBARAM, Jeremy D. ECTON
  • Publication number: 20230101629
    Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
  • Publication number: 20230095281
    Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Kyle McElhinny, Hongxia Feng, Xiaoying Guo, Steve Cho, Jung Kyu Han, Changhua Liu, Leonel Arana, Rahul Manepalli, Dingying Xu, Amram Eitan
  • Publication number: 20230087367
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Applicant: Intel Corporation
    Inventors: Xiaoxuan Sun, Omkar G. Karhade, Dingying Xu, Sairam Agraharam, Xavier Francois Brun
  • Publication number: 20230089928
    Abstract: Semiconductor devices having hollow filler materials are disclosed. A disclosed example semiconductor device includes at least one of a substrate or an interposer, interconnects extending through the at least one of the substrate or the interposer, and a composite material integral with or covering at least a portion of the semiconductor device, the composite material including a polymer matrix with a hollow filler material having voids therein.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Ziyin Lin, Yiqun Bai, Hongxia Feng, Dingying Xu, Jieying Kong, Srinivas Pietambaram
  • Publication number: 20220399263
    Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Tarek A. Ibrahim, Karumbu Nathan Meyyappan, Valery Ouvarov-Bancalero, Dingying Xu
  • Patent number: 11340258
    Abstract: A prober head to interface an E-testing apparatus to a device under test, which may be an unpackaged die, for example. In some embodiments, the prober head includes an array of conductive pins, each of the pins extending outwardly from a first pin end anchored to a substrate. At least a partial length of each of the pins is coated with a hydrophobic monolayer. The conductive pins may be composite metal wires including a core metal encased by one or more peripheral metal. At a tip of the pins, opposite the first pin end anchored to the substrate, the peripheral metals are recessed from the core metal. In further embodiments, the hydrophobic monolayer is disposed on an outer surface of the peripheral metals, but is substantially absent from a surface of the core metal exposed at the tip.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Joseph D. Stanford, David Craig, Todd P. Albertson, Mohit Mamodia, Dingying Xu
  • Publication number: 20220102259
    Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Jieying Kong, Yiyang Zhou, Suddhasattwa Nad, Jeremy Ecton, Hongxia Feng, Tarek Ibrahim, Brandon Marin, Zhiguo Qian, Sarah Blythe, Bohan Shan, Jason Steill, Sri Chaitra Jyotsna Chavali, Leonel Arana, Dingying Xu, Marcel Wall
  • Publication number: 20220102242
    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Applicant: Intel Corporation
    Inventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
  • Publication number: 20210318612
    Abstract: The present disclosure is directed to a patterning process that includes providing a composite dry film resist on a surface, in which the composite dry film resist includes a base film, a barrier layer and a resist layer, in which the base film is disposed over the barrier layer and the barrier layer is disposed over the resist layer. In another aspect, the patterning process includes removing the base film from the barrier layer and exposing the barrier layer to form an exposure precursor, which has a first area and a second area, further exposing the first area of the exposure precursor to electromagnetic irradiation, which passes through the barrier layer and the resist layer in the exposed first area becomes water-insoluble, and removing the barrier layer and the unexposed second area to form a pattern template.
    Type: Application
    Filed: June 24, 2021
    Publication date: October 14, 2021
    Inventors: Hongxia FENG, Changhua LIU, Bohan SHAN, Dingying XU, Leonel ARANA, Manuel GADOGBE, Matthew TINGEY, Julianne TROIANO
  • Publication number: 20200312771
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN