Patents by Inventor Dingying Xu

Dingying Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12354883
    Abstract: Various embodiments disclosed relate to methods of making omni-directional semiconductor interconnect bridges. The present disclosure includes semiconductor assemblies including a mold layer having mold material, a first filler material dispersed in the mold material, and a second filler material dispersed in the mold material, wherein the second filler material is heterogeneously dispersed.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: July 8, 2025
    Assignee: Intel Corporation
    Inventors: Bohan Shan, Dingying Xu, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Jung Kyu Han, Xiaoying Guo, Jeremy D. Ecton, Santosh Tripathi, Bai Nie, Haobo Chen, Kyle Jordan Arrington, Yue Deng, Wei Wei
  • Publication number: 20250219021
    Abstract: In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.
    Type: Application
    Filed: December 27, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Ziyin Lin, Ryan Joseph Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Yiqun Bai, Kyle J. Arrington, Jose Fernando Waimin Almendares, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Brandon Christian Marin, Clay Bradley Arrington, Yongki Min, Joseph Allen Van Nausdle, Joseph F. Walczyk, Pooya Tadayon, Mohamed R. Saber
  • Publication number: 20250218880
    Abstract: Methods for fabricating glass cores with conductive vias (e.g., TGVs), as well as related devices, are disclosed. Methods described herein are based on fabricating pillars of conductive materials (e.g., metals or metal alloys) on a temporary support, inserting the pillars into corresponding via openings in a glass core, and at least partially filling the remaining space in the openings with a filler material.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Jose Waimin, Ryan Carrazzone, Bin Mu, Ziyin Lin, Yiqun Bai, Kyle Jordan Arrington, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Dingying Xu, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo
  • Publication number: 20250218904
    Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. A spacer may be included between the power components. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Bohan Shan, Kyle J. Arrington, Ryan Joseph Carrazzone, Jose Fernando Waimin Almendares, Hongxia Feng, Srinivas Venkata Ramanuja Pietambaram, Hiroki Tanaka, Haobo Chen, Gang Duan, Brandon Christian Marin, Yongki Min, Dingying Xu, Clay Bradley Arrington, Jeremy D. Ecton, Suddhasattwa Nad
  • Publication number: 20250219028
    Abstract: An apparatus is provided which comprises: a substrate core comprising a first core layer bonded with a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and wherein the first circuit component comprises a deep trench capacitor, and one or more integrated circuit devices coupled with a second redistribution layers surface opposite the first redistribution layers surface. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Bohan Shan, Numair Ahmed, Nevin Erturk, Ziyin Lin, Ryan Carrazzone, Hongxia Feng, Hiroki Tanaka, Haobo Chen, Kyle Arrington, Jose Waimin, Srinivas Pietambaram, Gang Duan, Dingying Xu, Mohit Gupta, Brandon Marin, Xiaoying Guo, Clay Arrington
  • Publication number: 20250210398
    Abstract: In some embodiments, a patternable TBDB for assembling 3D assemblies such as IC/optical assemblies are provided. A patternable TBDB adhesive may be formed using silicone based TBDB adhesives with incorporated photocatalysts to allow for patterning of the TBDB adhesive layer.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Inventors: Clay ARRINGTON, Bohan SHAN, Dingying XU, Jonas CROISSANT, Xavier BRUN, Jigneshkumar PATEL
  • Publication number: 20250210426
    Abstract: Various techniques for alleviating crack formation and propagation in glass cores of microelectronic assemblies, and related devices and methods, are disclosed. The techniques are based on including fillers into glass cores and/or in layers provided on top and/or bottom of glass cores. The fillers have at least one characteristic indicative of material's resistance to breaking under stress being higher than that of glass, which may provide reinforcement and/or increase stiffness of glass, thereby strengthening glass cores. Examples of such characteristics include material strength, fracture toughness, or elastic modulus.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Mahdi Mohammadighaleni, Hiroki Tanaka, Kyle Jordan Arrington, Yiqun Bai, Whitney Bryks, Ryan Carrazzone, Haobo Chen, Gang Duan, Jeremy Ecton, Hongxia Feng, Xiaoying Guo, Shayan Kaviani, Ziyin Lin, Brandon C. Marin, Robert Alan May, Bin Mu, Bai Nie, Ala Omer, Srinivas Venkata Ramanuja Pietambaram, Dilan Seneviratne, Jose Waimin, Dingying Xu, Ehsan Zamani
  • Publication number: 20250183182
    Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.
    Type: Application
    Filed: November 30, 2023
    Publication date: June 5, 2025
    Inventors: Bohan Shan, Mahdi Mohammadighaleni, Joshua Stacey, Ehsan Zamani, Aaditya Candadai, Jacob Vehonsky, Daniel Wandera, Mitchell Page, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jeremy Ecton, Brandon C. Marin, Onur Ozkan, Vinith Bejugam, Dhruba Pattadar, Amm Hasib, Nicholas Haehn, Makoyi Watson, Sanjay Tharmarajah, Jason M. Gamba, Yuqin Li, Astitva Tripathi, Mohammad Mamunur Rahman, Haifa Hariri, Shayan Kaviani, Logan Myers, Darko Grujicic, Elham Tavakoli, Whitney Bryks, Dilan Seneviratne, Bainye Angoua, Peumie Abeyratne Kuragama, Hongxia Feng, Kyle Jordan Arrington, Bai Nie, Jose Waimin, Ryan Carrazzone, Haobo Chen, Dingying Xu, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Bin Mu, Thomas S. Heaton, Rahul N. Manepalli
  • Publication number: 20250110295
    Abstract: A set of optical fibers are set within grooves a substrate to align the optical fibers with a waveguide associated with photonic processing circuitry. The set of optical fibers are adhered within the grooves using a polyethylene oxide (PEO)-based adhesive. The PEO-based adhesive may have a refractive index matched to the refractive index of one or both of the optical fibers or the waveguide.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Saikumar Jayaraman, Yiqun Bai, Fan Fan, Dingying Xu
  • Publication number: 20250112085
    Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, organic dielectric material over the plurality of interconnect layers, copper pads on a surface of a cavity within the organic dielectric material, an integrated circuit bridge device coupled with the copper pads, wherein a surface of the integrated circuit bridge device is elevated above an opening of the cavity, underfill material between the integrated circuit bridge device and the surface of the cavity, and build-up layers formed over the organic dielectric material around the integrated circuit bridge device. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Ziyin Lin, Haobo Chen, Yiqun Bai, Kyle Arrington, Jose Waimin, Ryan Carrazzone, Hongxia Feng, Dingying Xu, Srinivas Pietambaram, Minglu Liu, Seyyed Yahya Mousavi, Xinyu Li, Gang Duan, Wei Li, Bin Mu, Mohit Gupta, Jeremy Ecton, Brandon C. Marin, Xiaoying Guo, Ashay Dani
  • Publication number: 20250112161
    Abstract: Methods and apparatus to connect interconnect bridges to package substrates are disclosed. An example package substrate includes a dielectric layer including a cavity, a first contact pad positioned in the cavity, a first semiconductor die including a second contact pad and a third contact pad, the second contact pad positioned on a first surface of the first semiconductor die, the third contact pad positioned on a second surface of the first semiconductor die, the second surface opposite the first surface, the second contact pad coupled to the first contact pad, the third contact pad to be coupled to a second semiconductor die, and a non-conductive material surrounding the first contact pad and the second contact pad.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Minglu Liu, Seyyed Yahya Mousavi, Yingying Zhang, Gang Duan, Andrey Gunawan, Yosuke Kanaoka, Yiqun Bai, Ziyin Lin, Bohan Shan, Dingying Xu, Srinivas Pietambaram, Hong Seung Yeon
  • Publication number: 20250105074
    Abstract: Glass cores including protruding through glass vias and related methods are disclosed herein. An example substrate disclosed herein includes a glass core including a surface and a copper through glass via (TGV) extending through the glass core, the TGV including a protrusion extending from the surface.
    Type: Application
    Filed: December 11, 2024
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Bohan Shan, Haobo Chen, Wei Wei, Jose Fernando Waimin Almendares, Ryan Joseph Carrazzone, Kyle Jordan Arrington, Ziyin Lin, Dingying Xu, Hongxia Feng, Yiqun Bai, Hiroki Tanaka, Brandon Christian Marin, Jeremy Ecton, Benjamin Taylor Duong, Gang Duan, Srinivas Venkata Ramanuja Pietambaram, Rui Zhang, Mohit Gupta
  • Patent number: 12230564
    Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 18, 2025
    Assignee: Intel Corporation
    Inventors: Brandon Christian Marin, Tarek A. Ibrahim, Karumbu Nathan Meyyappan, Valery Ouvarov-Bancalero, Dingying Xu
  • Publication number: 20250006645
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Xiao Liu, Bohan Shan, Dingying Xu, Gang Duan, Haobo Chen, Hongxia Feng, Jung Kyu Han, Xiaoying Guo, Zhixin Xie, Xiyu Hu, Robert Alan May, Kristof Kuwawi Darmawikarta, Changhua Liu, Yosuke Kanaoka
  • Publication number: 20240395567
    Abstract: Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.
    Type: Application
    Filed: May 25, 2023
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Jonas G. Croissant, Yiqun Bai, Dingying Xu, Xavier F. Brun, Timothy Gosselin, Ye Seul Nam, Gustavo Arturo Beltran, Roberto Serna, Jesus S. Nieto Pescador, Aris Mercado Orbase
  • Publication number: 20240332125
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a first layer and a second layer over the first layer. In an embodiment, the second layer comprises a dielectric material including sulfur. In an embodiment, fillers are within the second layer. In an embodiment, the fillers have a volume fraction that is less than approximately 0.2.
    Type: Application
    Filed: March 30, 2023
    Publication date: October 3, 2024
    Inventors: Kyle ARRINGTON, Clay ARRINGTON, Bohan SHAN, Haobo CHEN, Srinivas V. PIETAMBARAM, Gang DUAN, Ziyin LIN, Hongxia FENG, Yiqun BAI, Xiaoying GUO, Dingying XU, Bai NIE
  • Publication number: 20240327679
    Abstract: This disclosure describes systems, methods, and devices related to switchable adhesion. A switchable adhesion system may comprise a shape memory polymer having a shaped surface to enhance adhesion using a trigger and a force applied to the shape memory polymer, wherein the trigger is applied to alter characteristics of the shape memory polymer, and wherein the force is applied to deform the shape memory polymer while the trigger is applied. The system may further comprise a media tray connected to the shape memory polymer.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Yuan MENG, Elizabeth NOFEN, Zhixin XIE, Dingying XU, Seyed Hadi ZANDAVI
  • Publication number: 20240312865
    Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Kyle Arrington, Bohan Shan, Haobo Chen, Bai Nie, Srinivas Pietambaram, Gang Duan, Ziyin Lin, Hongxia Feng, Yiqun Bai, Xiaoying Guo, Dingying Xu
  • Patent number: 12068222
    Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 20, 2024
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
  • Publication number: 20240270929
    Abstract: Capillary underfill formulations that may include fillers. The fillers may include carbon nanotubes, such as surface functionalized carbon nanotubes. Methods for forming capillary underfill materials that may have improved fracture toughness, reduced crack propagation, and a reduced likelihood of delamination. The surface functionalized carbon nanotubes may include amine functionalized carbon nanotubes. Containers, such as syringes, that may have a reservoir in which a capillary underfill formulation is disposed.
    Type: Application
    Filed: February 8, 2023
    Publication date: August 15, 2024
    Inventors: Clay Arrington, Kyle Arrington, Ziyin Lin, Jose Waimin, Dingying Xu