Abstract: A copper pillar bump structure on a copper pillar on a metal pad of a semiconductor device and a method of fabricating thereof are disclosed. The copper pillar bump structure includes: a metal barrier layer formed on the copper pillar. The metal barrier layer has a U-shaped cross section, a central portion of the metal barrier layer covers the top surface of the copper pillar, an opening of the U-shaped cross section faces away from the copper pillar. The copper pillar bump structure further includes a solder layer on the copper pillar and filling the U-shaped cross section. The copper pillar bump structure provides a metal barrier layer having a U-shaped cross section and fills a solder layer in the U-shaped cross section, the metal barrier layer wraps sides of the solder layer, which can improve the non-wetting problem caused by insufficient tin, or the solder bridging problem caused by excessive solder, during a flip die soldering process.

Abstract: The present invention provides a wafer, semiconductor device and a method for manufacturing the same, in relation to the field of semiconductor technology. The wafer includes: a substrate; a dielectric layer, disposed on a surface of the substrate; a wafer acceptance test circuit, formed in the dielectric layer; a trench, formed in the dielectric layer and situated on a side of the wafer acceptance test circuit. The wafer acceptance test circuit may comprise a metal interconnection layer. The trench may be filled with a protective layer and has a depth greater than or equal to a depth of the wafer acceptance test circuit. When dicing dies along the scribe line area, the stress caused by dicing can be buffered and cracks may be reduced due to the elasticity of the protective layer. Moreover, the trench and the protective layer filled in the trench can prevent the cracks from extending, thereby improving the yield and stability of the dies.

Abstract: A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.

Abstract: An asymmetric fin field-effect transistor (FinFET) in a memory device, a method for fabricating the FinFET and a semiconductor device are disclosed. In the provided FinFET and method, each of the active areas comprises a fin, a length of a first end of the fin on a first side of the active area and covered by the word line being different from a length of a second end of the fin on a second side of the active area and covered by the word line. For this reason, the present invention allows reduced process difficulty. In addition, the different lengths of the word lines can induce a weaker unidirectional electric field which suffers from much less current leakage, compared to a bidirectional electric field created in word lines with equal such length.

Abstract: A chip molding structure, a wafer level chip scale packaging structure and manufacturing methods thereof are disclosed, relating to the technical field of semiconductor production. The method of making a wafer level chip scale packaging structure includes: providing a wafer, comprising a plurality of bottom chips; bonding the wafer with a carrier; dicing the wafer to separate the plurality of bottom chips from a plurality of peripheral portions; removing the plurality of peripheral portions; and molding the plurality of bottom chips with a mold to form the molding structure. By dicing the wafer into independent bottom chips and peripheral portions, with the peripheral portions being removed before molding, the bottom chips may be prevented from being damaged during the molding. Compared with existing technologies, the packaging quality and production yield are improved.

Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a semiconductor substrate including island patterns and trenches alternately arranged in a semiconductor substrate, wherein an upper surface of the island pattern close to a corresponding one of the trenches is a corner area; a patterned liner oxide layer covering an area of the upper surface of the island pattern except the corner area; and a protective layer covering the sidewalls and the bottom surface of the trench, the corner area and the side surface of the patterned liner oxide layer, wherein the protective layer extends from the sidewall of the trench to the corner area to form a corner; and an isolation structure located within each of the trenches. An area of the island pattern near the corner may be prevented from being oxidized.

Abstract: A copper pillar bump structure on a copper pillar on a metal pad of a semiconductor device and a method of fabricating thereof are disclosed. The copper pillar bump structure includes: a metal barrier layer formed on the copper pillar. The metal barrier layer has a U-shaped cross section, a central portion of the metal barrier layer covers the top surface of the copper pillar, an opening of the U-shaped cross section faces away from the copper pillar. The copper pillar bump structure further includes a solder layer on the copper pillar and filling the U-shaped cross section. The copper pillar bump structure provides a metal barrier layer having a U-shaped cross section and fills a solder layer in the U-shaped cross section, the metal barrier layer wraps sides of the solder layer, which can improve the non-wetting problem caused by insufficient tin, or the solder bridging problem caused by excessive solder, during a flip die soldering process.

Abstract: The present invention provides a wafer, semiconductor device and a method for manufacturing the same, in relation to the field of semiconductor technology. The wafer includes: a substrate; a dielectric layer, disposed on a surface of the substrate; a wafer acceptance test circuit, formed in the dielectric layer; a trench, formed in the dielectric layer and situated on a side of the wafer acceptance test circuit. The wafer acceptance test circuit may comprise a metal interconnection layer. The trench may be filled with a protective layer and has a depth greater than or equal to a depth of the wafer acceptance test circuit. When dicing dies along the scribe line area, the stress caused by dicing can be buffered and cracks may be reduced due to the elasticity of the protective layer. Moreover, the trench and the protective layer filled in the trench can prevent the cracks from extending, thereby improving the yield and stability of the dies.

Abstract: An asymmetric fin field-effect transistor (FinFET) in a memory device, a method for fabricating the FinFET and a semiconductor device are disclosed. In the provided FinFET and method, each of the active areas comprises a fin, a length of a first end of the fin on a first side of the active area and covered by the word line being different from a length of a second end of the fin on a second side of the active area and covered by the word line. For this reason, the present invention allows reduced process difficulty. In addition, the different lengths of the word lines can induce a weaker unidirectional electric field which suffers from much less current leakage, compared to a bidirectional electric field created in word lines with equal such length.

Abstract: A memory transistor comprises a substrate comprising a first surface and a second surface opposing the first surface, the substrate further comprising a first trench having an opening formed in the first surface; a first dielectric layer formed on an inner surface of the first trench; a gate layer formed on the first dielectric layer in the first trench, the gate layer having a top surface lower than the first surface; and a second dielectric layer filled in the first trench and located on the top surface of the gate layer, the second dielectric layer covering the gate layer and connecting to the first dielectric layer, the second dielectric layer having a cavity formed therein.