Abstract: The present invention relates to semiconductor devices and integrated circuit packaging. In a specific embodiment, a semiconductor device comprising a double-sided fanout die package is provided. On one surface of a main circuit board for the semiconductor device, regular single-sided flip-chip dies and tall SMT components are coupled, along with one or more double-sided fanout dies, which are stacked with corresponding sub-sized circuit boards that are also coupled to the same surface, with a smaller height than the tallest surface mount device. A portion of the metal routing and grounding connections in the main circuit board for one or more double-sided fanout dies can be transferred to the sub-sized circuit boards, thereby reducing the area of the main circuit board without increasing the number of circuit board layers. There are other embodiments as well.

Abstract: A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

Abstract: An apparatus includes a first substrate comprising one or more first interconnection layers, wherein a first die is coupled to a first side of the first substrate, and a second substrate comprising one or more second interconnection layers. The second die may be coupled to a first side of the second substrate, and a third die is coupled to a second side of the second substrate. The first substrate and the second substrate may be stacked together.

Abstract: An electronic device includes a printed circuit board (PCB) defining a cavity, a first component pad of the PCB positioned outside the cavity, and a second component pad of the PCB positioned on a bottom surface of the cavity. The first component pad has a first thickness, and the second component pad has a second thickness that is less than the first thickness of the first component pad. An electronic component, such as a surface mounted technology (SMT) component, is mounted to the second component pad within the cavity.

Abstract: An electronic device includes a printed circuit board (PCB) defining a cavity, a first component pad of the PCB positioned outside the cavity, and a second component pad of the PCB positioned on a bottom surface of the cavity. The first component pad has a first thickness, and the second component pad has a second thickness that is less than the first thickness of the first component pad. An electronic component, such as a surface mounted technology (SMT) component, is mounted to the second component pad within the cavity.

Abstract: Methods and structures for fabricating conductive vias in circuit structures are provided. Methods may include, for example, providing a substrate that includes a dopant and at least one trench formed in the substrate; providing an undoped semiconductor layer over a surface of the substrate within the trench; and providing a conductive material on top of dielectric layer in the trench, the conductive material forming the conductive via. The undoped semiconductor layer, having no dopant, reduces a parasitic capacitance between the conductive via and the substrate. The undoped semiconductor layer may also prevent migration of dopant from the substrate into the undoped semiconductor layer, further reducing capacitance in the circuit structure.