Abstract: The presently claimed invention provides a layered catalytic article comprising a first layer comprising a nickel component and a ceria component, wherein the amount of the nickel component is 1.0 to 50 wt. %, calculated as nickel oxide, based on the total weight of the first layer, and wherein the first layer is essentially free of copper; a second layer comprising a platinum group metal component, an oxygen storage component, and an alumina component, wherein the platinum group metal component comprises platinum, rhodium, palladium, or any combination thereof, and wherein the amount of the platinum group metal component is 0.0 to 5 wt. %, based on the total weight of the second layer; and a substrate. The presently claimed invention also provides a process for preparing the layered catalytic article. It further provides an exhaust system for internal combustion engines comprising a layered catalytic article.

Abstract: The presently claimed invention provides a layered catalytic article comprising a first layer comprising a nickel component and a ceria component, wherein the amount of the nickel component is 1.0 to 50 wt. %, calculated as nickel oxide, based on the total weight of the first layer, and wherein the first layer is essentially free of copper; a second layer comprising a platinum group metal component, an oxygen storage component, and an alumina component, wherein the platinum group metal component comprises platinum, rhodium, palladium, or any combination thereof, and wherein the amount of the platinum group metal component is 0.0 to 5 wt. %. based on the total weight of the second layer; and a substrate. The presently claimed invention also provides a process for preparing the layered catalytic article. It further provides an exhaust system for internal combustion engines comprising a layered catalytic article.

Abstract: Provided are automotive catalyst composites having a catalytic material on a carrier, wherein the catalytic material comprises at least two layers. The first layer is deposited directly on the carrier and comprises a first palladium component supported on a first refractory metal oxide component, a first oxygen storage component, or a combination thereof. The second layer is deposited on top of the first layer and comprises a rhodium component supported on a second refractory metal oxide component and a second palladium component supported on a second oxygen storage component, a third refractory metal oxide component or a combination thereof. Generally these catalyst composites are used as three-way conversion (TWC) catalysts. Methods of making and using the same are also provided.

Abstract: Provided are automotive catalyst composites having a catalytic material on a carrier, wherein the catalytic material comprises at least two layers. The first layer is deposited directly on the carrier and comprises a first palladium component supported on a first refractory metal oxide component, a first oxygen storage component, or a combination thereof. The second layer is deposited on top of the first layer and comprises a rhodium component supported on a second refractory metal oxide component and a second palladium component supported on a second oxygen storage component, a third refractory metal oxide component or a combination thereof. Generally these catalyst composites are used as three-way conversion (TWC) catalysts. Methods of making and using the same are also provided.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract: A method of making a semiconductor structure includes forming a trench through a shallow trench isolation (STI) structure and into a substrate, and forming a liner including an electrical insulator material on sidewalls of the trench. The method also includes forming a core including a high thermal conductivity material in the trench and on the liner, and forming a cap in the trench and on the core.

Abstract: A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A semiconductor structure. A hard mask layer is on a top substrate surface of a semiconductor substrate. The hard mask layer includes a hard mask layer opening through which a portion of the top substrate surface is exposed to a surrounding ambient. The hard mask layer includes a pad oxide layer on the top substrate surface, a nitride layer on the pad oxide layer, a BSG (borosilicate glass) layer on top of the nitride layer, and an ARC (anti-reflective coating) layer on top of the BSG layer. A BSG side wall surface of the BSG layer is exposed to the surrounding ambient through the hard mask layer opening.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.