Abstract: A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

Abstract: A microprocessor system having a first read path from memory and a second read path from peripheral units and an isolation buffer to isolate the first read path from the second read path. The system also has a first write path to memory and a second write path to peripheral units and an isolation buffer to isolate the first write path from the second write path. The isolation buffers also isolate the write paths from the read paths. Also included is a monitoring path between the peripherals and an external bus to allow program monitoring of data in the peripheral units.