Patents by Inventor Dinkar Virendra Singh

Dinkar Virendra Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Selective incorporation of charge for transistor channels
    Patent number: 7687863
    Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: March 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
  • SELECTIVE INCORPORATION OF CHARGE FOR TRANSISTOR CHANNELS
    Publication number: 20080217682
    Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
    Type: Application
    Filed: May 16, 2008
    Publication date: September 11, 2008
    Inventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight
  • Selective incorporation of charge for transistor channels
    Patent number: 7374998
    Abstract: A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: John Michael Hergenrother, Zhibin Ren, Dinkar Virendra Singh, Jeffrey William Sleight