Abstract: Remote electronic units effective to generate output data for an actuator are described. A remote electronic unit may include first, second, and third lanes. The first, second, and third lanes may receive input data including an actuator command. The first, second, and third lanes may generate first, second, and third output data, respectively, based on the input data. The first, second, and third lanes may respectively send the first, second, and third output data to a voter. The first and second lanes may respectively send the first and second output data to a multiplexer. The voter may output a selection signal to the multiplexer if at least two out of the first, second, and third output data are identical. The multiplexer may select one of the first and the second output data based on the selection signal and transmit the selection to the actuator via an actuator control electronics.

Abstract: A control system includes a computing channel and an object control channel. The computing channel includes command and monitor lanes. The command lane has a first processor core with a first core architecture receiving input data and generating first data based on the input data. The monitor lane has a second processor core with second core architecture receiving the input data and generating second data based on the input data. The first core architecture and the second core architecture are dissimilar and implemented in a single system-on chip device. The computing channel outputs the first data as command data responsive to determining the first data is matched to the second data. The object control channel corresponds to the computing channel and includes an object control system receiving the command data and generating an object control signal based on the command data to control operation of at least one part of an object system.

Abstract: A control system includes a computing channel and an object control channel. The computing channel includes command and monitor lanes. The command lane has a first processor core with a first core architecture receiving input data and generating first data based on the input data. The monitor lane has a second processor core with second core architecture receiving the input data and generating second data based on the input data. The first core architecture and the second core architecture are dissimilar and implemented in a single system-on chip device. The computing channel outputs the first data as command data responsive to determining the first data is matched to the second data. The object control channel corresponds to the computing channel and includes an object control system receiving the command data and generating an object control signal based on the command data to control operation of at least one part of an object system.

Abstract: A plurality of control channels each include a power supply, an interface that receives a manipulation signal, an arithmetic processing portion that calculates and generates an operation command signal for actuators based on the manipulation signal, and a signal determination unit that determines a control signal for finally controlling the operation of the actuators and outputs the control signal. The arithmetic processing portions respectively provided in the plurality of control channels have designs different from one another. Each of the signal determination units determines the control signal by receiving a first operation command signal generated by the arithmetic processing portion of the control channel in which that signal determination unit is provided, and a second operation command signal generated in the arithmetic processing portion of another of the control channels, and comparing the first operation command signal and the second operation command signal, and outputs the control signal.

Abstract: Various embodiments of the present invention relate to use of one or more multicore processors for network communication (e.g., Ethernet-based communication) in control systems (e.g., vehicle control systems, medical control systems, hospital control systems, instrumentation control systems, test instrument control systems, energy control systems and/or industrial control systems). In one example, one or more systems may be provided with regard to use of multicore processor(s) for network communication (e.g., Ethernet-based communication) in control systems. In another example, one or more methods may be provided with regard to use of multicore processor(s) for network communication (e.g., Ethernet-based communication) in control systems.

Abstract: Various embodiments of the present invention relate to a Unified Memory Architecture. The Unified Memory Architecture may use MRAM, phase change memory, and/or any other storage having similar features.