Abstract: A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

Abstract: A method of constructing a waveform from N sampled data captured at N successive points in time, includes, in part, applying the N sampled data, K data at a time, to each of M delayed replicas of a filter that includes K taps so to generate N×M interpolated data. The waveform is then constructed from the N sampled data and the N×M interpolated data.

Abstract: A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.

Abstract: Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation.

Abstract: Disclosed is a calibration unit for calibrating an oscillator of a device comprises a counting and comparing unit and a control circuit. The counting and comparing unit is configured to determine a number of periods of a clock signal lying between a starting instance and an ending instance. Therein, the clock signal is generated by the oscillator. The counting and comparing unit is further configured to determine a deviation of the number of periods from a reference number. The control circuit is configured to adjust the oscillator depending on the deviation.

Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

Abstract: A “supply-less” transmitter output stage is provided for a transmitter. This transmitter output stage can include a tunable source termination and a reference voltage generator. The tunable source termination can be coupled between a differential pair of the transmitter. The reference voltage generator can advantageously generate reference voltages from a far-end termination. These reference voltages provide a way of translating the internal supply voltage level to the pad voltage level to enable/disable the tunable source termination. Also, it provides a way to minimize leakage and minimize the junction stress of switching transistors in the tunable source termination as well as the transmitter. The dependency between the reference voltages and the far-end termination voltage makes this design more portable to other supply voltages and other technologies specifications other than HDMI.

Abstract: Embodiments of the present invention provide a voltage regulator. The voltage regulator includes a driving mechanism coupled to an output node (VREG), wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node. In addition, the voltage regulator includes a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in the output node voltage when a load coupled to the output node requires a transient switching current that is faster than the loop response time of the driving mechanism. Furthermore, the boost circuit is biased using a self-tracking mechanism to provide accurate duration and level of the current to the output node in a transient switching event.

Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45?±10%) in the USB transceiver.

Abstract: A “supply-less” transmitter output stage is provided for a transmitter. This transmitter output stage can include a tunable source termination and a reference voltage generator. The tunable source termination can be coupled between a differential pair of the transmitter. The reference voltage generator can advantageously generate reference voltages from a far-end termination. These reference voltages provide a way of translating the internal supply voltage level to the pad voltage level to enable/disable the tunable source termination. Also, it provides a way to minimize leakage and minimize the junction stress of switching transistors in the tunable source termination as well as the transmitter. The dependency between the reference voltages and the far-end termination voltage makes this design more portable to other supply voltages and other technologies specifications other than HDMI.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 ?±10%) in the USB transceiver.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45?±10%) in the USB transceiver.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45?±10%) in the USB transceiver.

Abstract: Embodiments of the present invention provide a system that controls noise in a power system that includes a power rail and a ground rail. The system includes a MOS transistor coupled in series with a decoupling capacitor between the power rail and the ground rail and an inductive packaging connection coupled to the power rail in parallel with the MOS transistor and the decoupling capacitor. The combination of MOS transistor, decoupling capacitor, and inductive packaging connection form a resonant circuit. During operation, the system determines if there is noise in a Vdd signal on the power rail. Based on the noise present in the Vdd signal, the system adjusts the impedance of the MOS transistor to reduce the noise in a frequency range near a frequency of interest (?interest) of the resonant circuit without causing an unnecessary increase in switching noise at other frequencies.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 ?±10%) in the USB transceiver.

Abstract: Embodiments of the present invention provide a voltage regulator. The voltage regulator includes a driving mechanism coupled to an output node (VREG), wherein the driving mechanism is configured to provide current to the output node to sustain a predetermined voltage on the output node. In addition, the voltage regulator includes a boost circuit coupled to the output node, wherein the boost circuit is configured to drive an additional current onto the output node to reduce fluctuations in the output node voltage when a load coupled to the output node requires a transient switching current that is faster than the loop response time of the driving mechanism. Furthermore, the boost circuit is biased using a self-tracking mechanism to provide accurate duration and level of the current to the output node in a transient switching event.

Abstract: Embodiments of the present invention provide a system that controls noise in a power system that includes a power rail and a ground rail. The system includes a MOS transistor coupled in series with a decoupling capacitor between the power rail and the ground rail and an inductive packaging connection coupled to the power rail in parallel with the MOS transistor and the decoupling capacitor. The combination of MOS transistor, decoupling capacitor, and inductive packaging connection form a resonant circuit. During operation, the system determines if there is noise in a Vdd signal on the power rail. Based on the noise present in the Vdd signal, the system adjusts the impedance of the MOS transistor to reduce the noise in a frequency range near a frequency of interest (?interest) of the resonant circuit without causing an unnecessary increase in switching noise at other frequencies.

Abstract: A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.

Abstract: A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS cascode transistor during normal operation such that the pullup resistance matches the pulldown resistance, and turns off the PMOS cascode transistor to shut off the pullup path during a 5V short condition. N-wells of the PMOS pullup and cascode transistors are connected to the 3.3V supply via a resistor.