Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A system and method which compensates for phase mixer circuit non-linearities within a clock and data recovery (CDR) system during active operation. The CDR system includes compensation circuitry and phase accumulation circuitry. The compensation circuitry generates a first compensation signal based on a first compensation value. The phase accumulation circuitry receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuitry combines the first compensation signal with the phase accumulator input update signal to compensate for a first non-linearity within phase mixer (PMI) circuitry.

Abstract: Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known relationship with a second voltage value that is used as a reference voltage in the second device. The offset circuitry can then determine the second voltage value from the second voltage signal, and output an offset value based on a difference between the first voltage value and the second voltage value.

Abstract: Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known relationship with a second voltage value that is used as a reference voltage in the second device. The offset circuitry can then determine the second voltage value from the second voltage signal, and output an offset value based on a difference between the first voltage value and the second voltage value.

Abstract: Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known relationship with a second voltage value that is used as a reference voltage in the second device. The offset circuitry can then determine the second voltage value from the second voltage signal, and output an offset value based on a difference between the first voltage value and the second voltage value.

Abstract: Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f1, and the second node can output a second signal having frequency f2 that is different from f1. In some embodiments, a frequency divider can generate a third signal having frequency f3 based on the second signal. In some embodiments, a frequency divider can generate the first signal based on a reference signal having frequency f4. The programmable phase rotator can be capable of updating, at an update frequency that is substantially equal to f1 and/or f4, a phase difference between the first signal and the second signal. In some embodiments, the circuit can be part of a USB (Universal Serial Bus) 3.0 physical layer (PHY) circuit.

Abstract: Methods and systems are described for monitoring and compensating an offset between a reference voltage used in a first device and a corresponding reference voltage used in a second device. The first device can include offset circuitry. The offset circuitry receives two voltage signals. The first voltage signal is equal to a first voltage value that is used as a reference voltage in the first device. The second voltage signal can be a time-varying voltage signal that has a known relationship with a second voltage value that is used as a reference voltage in the second device. The offset circuitry can then determine the second voltage value from the second voltage signal, and output an offset value based on a difference between the first voltage value and the second voltage value.

Abstract: Circuits and systems for generating multiple frequencies are disclosed. In some embodiments, a circuit can include a first node, a second node, and a programmable phase rotator. The first node can receive a first signal having frequency f1, and the second node can output a second signal having frequency f2 that is different from f1. In some embodiments, a frequency divider can generate a third signal having frequency f3 based on the second signal. In some embodiments, a frequency divider can generate the first signal based on a reference signal having frequency f4. The programmable phase rotator can be capable of updating, at an update frequency that is substantially equal to f1 and/or f4, a phase difference between the first signal and the second signal. In some embodiments, the circuit can be part of a USB (Universal Serial Bus) 3.0 physical layer (PHY) circuit.

Abstract: Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit.

Abstract: Embodiments of the present invention provide a system for controlling a startup time of an oscillator circuit. The system includes a variable current source coupled to the oscillator circuit, wherein a startup time of the oscillator circuit is proportional to a bias current input into the oscillator circuit from the variable current source. The system also includes a control mechanism coupled to the variable current source and to the output of the oscillator circuit. Upon startup, the control mechanism is configured to adjust the variable current source to input a large startup bias current into the oscillator circuit. After the oscillator circuit outputs a predetermined number of oscillations during startup, the control mechanism is configured to adjust the variable current source to decrease its current to a smaller steady-state bias current into the oscillator circuit.