Abstract: A three-phase load is powered by an SPWM driven inverter having a single shunt-topology. During operation, drain-to-source resistances of transistors of each branch of the inverter are determined. Interpolation is performed on assumed drain-to-source resistances of the transistors for different temperatures to produce a non-linear model of drain-to-source resistance to temperature for the transistors, and the drain-to-source resistances determined during operation and the non-linear model are used to estimate temperature values of the transistors. Driving of the inverter can be adjusted so that conductivity of each branch is set so that power delivered by that branch is as high as possible without exceeding an allowed drain current threshold representing a threshold junction temperature. In addition, driving of the inverter can be ceased if the temperature of a transistor exceeds the threshold temperature.

Abstract: An apparatus includes a first inverter configured to drive a first motor having a plurality of phases, the first inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the first motor, a second inverter configured to drive a second motor having a plurality of phases, the second inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the second motor, and a first current sensor configured to sense currents flowing in the first inverter and the second inverter, wherein the first current sensor is shared by at least by two inverter legs.

Abstract: An apparatus includes a first inverter configured to drive a first motor having a plurality of phases, the first inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the first motor, a second inverter configured to drive a second motor having a plurality of phases, the second inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the second motor, and a first current sensor configured to sense currents flowing in the first inverter and the second inverter, wherein the first current sensor is shared by at least by two inverter legs.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

Abstract: An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.

Abstract: An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.

Abstract: An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.

Abstract: An estimate of the initial position of a rotor is made by monitoring sensed motor current signals which are amplitude and phase modulated with the rotor flux position in response to a high frequency voltage signal injection. The motor current signals are envelope detected to determine zero crossing points. Samples are taken of the motor current signals at positive and negative offsets from the zero crossing point, with the samples processed to identify a direction of the rotor flux axis. Further samples of at least one motor current signal are taken with respect to a certain phase reference, and the samples compared to resolve a polarity of the rotor flux axis which is indicative of the angular position of the rotor.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: A method of controlling a synchronous motor that may include windings and a power driving stage coupled to the windings, may include using a feedback loop including using a feedback circuit coupled to the windings to generate current feedback components, using current controllers for generating respective voltage signals, and using an anti-transform circuit for generating control signals for the power driving stage. Using the feedback loop may include generating additional compensation signals for compensating the control signals, and adding the additional compensation signals from the current controllers by one of generating the additional compensation signals as quadrature and direct voltage compensation signals and adding them to the voltage signals to generate compensated quadrature and direct signals, and supplying the compensated quadrature and direct signals to the power driving stage by providing the compensated quadrature and direct signals to the anti-transform circuit.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

Abstract: An analog-to-digital converter device may include an input multiplexer circuit having analog input terminals configured to receive a respective plurality of analog input signals. The input multiplexer circuit may be responsive to a first select input. The device may also include a trigger multiplexer circuit having input terminals configured to receive respective triggering signals. The trigger multiplexer circuit may be responsive to a second select input. Analog-to-digital converter circuitry may be configured to convert the selected analog signal into a digital signal. A sequence arbiter may be coupled to the first and second select inputs and may have input terminals configured to receive a respective plurality of conversion sequence configuration signals. The sequence arbiter may be configured to manage each conversion sequence of the analog-to-digital converter circuitry based upon the relative conversion sequence configuration signal received, and control the conversion sequences.

Abstract: A method of controlling a synchronous motor that may include windings and a power driving stage coupled to the windings, may include using a feedback loop including using a feedback circuit coupled to the windings to generate current feedback components, using current controllers for generating respective voltage signals, and using an anti-transform circuit for generating control signals for the power driving stage. Using the feedback loop may include generating additional compensation signals for compensating the control signals, and adding the additional compensation signals from the current controllers by one of generating the additional compensation signals as quadrature and direct voltage compensation signals and adding them to the voltage signals to generate compensated quadrature and direct signals, and supplying the compensated quadrature and direct signals to the power driving stage by providing the compensated quadrature and direct signals to the anti-transform circuit.