Abstract: A data interface for CMOS imagers is disclosed that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.