Abstract: A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS cascode transistor during normal operation such that the pullup resistance matches the pulldown resistance, and turns off the PMOS cascode transistor to shut off the pullup path during a 5V short condition. N-wells of the PMOS pullup and cascode transistors are connected to the 3.3V supply via a resistor.

Abstract: A USB 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.

Abstract: A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D? signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 ?±10%) in the USB transceiver.

Abstract: A system of resistive end termination and transmission line routing is disclosed for matching the impedance of an IC load to that of a signal source and a transmission line. Each integrated circuit has an internal termination resistor designed to match the characteristic impedance of the transmission line and preferably also the impedance of the source. When the source drives multiple IC devices on a printed circuit board, the devices are cascaded in a chain with the internal resistors of all but the last IC device in the chain bypassed by a short circuit underneath the device, so that a continuous transmission line is provided to the last IC device. The last IC in the chain, which does not have a short circuit underneath it, provides the necessary resistive termination by simply connecting the appropriate pin to a common reference in the circuit. The invention is also applicable to differential applications in which first and second complementary signal sources feed each IC device.