Patents by Inventor Diong Hing Ding

Diong Hing Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450732
    Abstract: A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 20, 2022
    Assignee: SUZHOU TF-AMD SEMICONDUCTOR CO. LTD.
    Inventors: Zhe Liu, Borrong Huang, Hongjie Wang, Diong Hing Ding
  • Publication number: 20200286983
    Abstract: A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 10, 2020
    Inventors: Zhe LIU, BORRONG HUANG, HONGJIE WANG, DIONG HING DING
  • Patent number: 6632690
    Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: October 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Edward S. Alcid, Diong-Hing Ding
  • Publication number: 20030077852
    Abstract: A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.
    Type: Application
    Filed: February 5, 2002
    Publication date: April 24, 2003
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Edward S. Alcid, Diong-Hing Ding
  • Patent number: 6409070
    Abstract: A method of manufacturing a flip-chip semiconductor device by attaching a semiconductor die to a substrate using solder comprises the steps of applying a no-clean flux to the semiconductor die and the substrate; heating the solder and the flux in a furnace to bond the semiconductor die to the substrate; and underfilling between the semiconductor die and the substrate. While the solder and flux is being heated, a reducing atmosphere in the furnace is being measured to determine the moisture content. When the moisture content exceeds a threshold amount, a signal will be provided. A reflow furnace for practicing the method is also disclosed.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Raj N. Master, Mohammad Z. Khan, Maria G. Guardado, Diong Hing Ding, Junaida Abu Bakar