Patents by Inventor Dionisio Minopoli
Dionisio Minopoli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210406203Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.Type: ApplicationFiled: December 3, 2019Publication date: December 30, 2021Inventors: Dionisio Minopoli, Daniele Balluchi
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Publication number: 20210349830Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: ApplicationFiled: July 26, 2021Publication date: November 11, 2021Inventors: Daniele Balluchi, Dionisio Minopoli
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Publication number: 20210334205Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer read command comprising a physical address of data to be read from a memory device, wherein the physical address is indicated in at least a portion of a translation layer entry previously provided to the host system with a response to a host-resident translation layer write command and stored in a host-resident translation layer mapping table. The processing device further performs a read operation to read the data stored at the physical address from the memory device and sends, to the host system, the data from the physical address of the memory device.Type: ApplicationFiled: May 17, 2021Publication date: October 28, 2021Inventors: Daniele Balluchi, Dionisio Minopoli
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Patent number: 11132311Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: GrantFiled: December 4, 2019Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Patent number: 11074192Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: GrantFiled: October 17, 2019Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Daniele Balluchi, Dionisio Minopoli
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Patent number: 11036625Abstract: A processing device in a memory system receives, from a host system, a host-resident translation layer write command requesting that data associated with a logical block address be written to the memory device and that a physical address to which the data is written be returned in response and performs a write operation to write the data associated with the logical block address to the physical address of the memory device. The processing device updates a translation layer entry corresponding to the logical block address to include the physical address and sends, to the host system, a response to the host-resident translation layer write command, the response comprising the updated translation layer entry with the physical address. The host system can to store the updated translation layer entry with the physical address in a host-resident translation layer mapping table.Type: GrantFiled: April 24, 2020Date of Patent: June 15, 2021Assignee: Micron Technology, Inc.Inventors: Daniele Balluchi, Dionisio Minopoli
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Publication number: 20210089443Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Patent number: 10860474Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: GrantFiled: December 14, 2017Date of Patent: December 8, 2020Assignee: Micron Technology, Inc.Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Publication number: 20200104268Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: ApplicationFiled: December 4, 2019Publication date: April 2, 2020Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Patent number: 10592427Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: GrantFiled: August 2, 2018Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventors: Daniele Balluchi, Dionisio Minopoli
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Publication number: 20200050554Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: ApplicationFiled: October 17, 2019Publication date: February 13, 2020Inventors: Daniele Balluchi, Dionisio Minopoli
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Publication number: 20200042458Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.Type: ApplicationFiled: August 2, 2018Publication date: February 6, 2020Inventors: Daniele Balluchi, Dionisio Minopoli
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Patent number: 10534731Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: GrantFiled: March 19, 2018Date of Patent: January 14, 2020Assignee: Micron Technology, Inc.Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Publication number: 20190286586Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.Type: ApplicationFiled: March 19, 2018Publication date: September 19, 2019Inventors: Dionisio Minopoli, Gianfranco Ferrante, Antonino Caprí, Emanuele Confalonieri, Daniele Balluchi
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Publication number: 20190188124Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.Type: ApplicationFiled: December 14, 2017Publication date: June 20, 2019Inventors: Gianfranco Ferrante, Dionisio Minopoli
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Publication number: 20180158527Abstract: In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.Type: ApplicationFiled: January 30, 2018Publication date: June 7, 2018Inventors: Emanuele Confalonieri, Dionisio Minopoli
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Publication number: 20150095551Abstract: In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.Type: ApplicationFiled: September 30, 2013Publication date: April 2, 2015Applicant: Micron Technology, Inc.Inventors: Emanuele Confalonieri, Dionisio Minopoli
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Patent number: 8014208Abstract: Example embodiments for verifying an erase operation for a flash memory device may comprise, for one or more embodiments, utilizing program operation verification circuitry to verify, at least in part, the erase operation.Type: GrantFiled: January 22, 2009Date of Patent: September 6, 2011Assignee: Micron Technology, Inc.Inventors: Gianfranco Ferrante, Dionisio Minopoli, Angelo Avino
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Patent number: 7995365Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.Type: GrantFiled: May 1, 2009Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Elio D'Ambrosio, Ciro Chiacchio, Dionisio Minopoli